公开(公告)号：US12293804B2

公开(公告)日：2025-05-06

申请号：US18266610

申请日：2022-04-20

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Xiangshui Miao ,  Jiawei Fu ,  Yuhui He

IPC: G11C5/02 ,  G06N3/0464 ,  G11C5/06 ,  G06N3/045 ,  G06N3/063

Abstract: The disclosure provides a convolution operation accelerator and a convolution operation method and belongs to the field of microelectronic devices. Input data of each word line may be subjected to a multiply-accumulate operation together with two upper and lower layers of convolution kernel units, so that natural sliding of the convolution kernel units in a y direction in two-dimensional input is achieved. The oblique bit lines and multiple copies of a convolution kernel in each layer of a non-volatile memory array may enable a multiplication operation between one piece of input data and convolution kernel data at different positions in the same convolution kernel. In this way, the natural sliding of the convolution kernel units in an x direction in the two-dimensional input is achieved.

公开(公告)号：US11989644B2

公开(公告)日：2024-05-21

申请号：US17259191

申请日：2020-05-28

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Hao Tong ,  Qing Hu ,  Yuhui He ,  Xiangshui Miao

IPC: G06N3/0464 ,  G06N3/063 ,  G11C11/54 ,  G11C13/00

CPC classification number: G06N3/063 ,  G11C11/54 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/77

Abstract: The disclosure discloses a three-dimensional (3D) convolution operation device and method based on a 3D phase change memory, which includes a 3D phase change memory, an input control module, a setting module, and an output control module. By using the 3D phase change memory to perform 3D convolution operation, the phase change units on the same bit line constitute a convolution kernel. Based on the multilayer stack structure, the upper and lower electrodes of the 3D phase change memory serve as the information input terminal, and they are convolved after passing through the respective phase change unit arrays, and the result of the convolution operation is superposed on the middle electrode in the form of current, thereby obtaining the sum of the convolution calculation results of the input information of the upper and lower electrodes, such that the 3D convolution operation is completed in one step.

公开(公告)号：US11825756B2

公开(公告)日：2023-11-21

申请号：US17785916

申请日：2021-08-30

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Yi Li ,  Yuhui He ,  Yaoyao Fu ,  Xiaodi Huang ,  Xiangshui Miao

IPC: H10N70/00 ,  H10N70/20 ,  H10B63/00

CPC classification number: H10N70/826 ,  H10B63/22 ,  H10B63/84 ,  H10N70/026 ,  H10N70/245

Abstract: The present invention provides a preparation method of a bipolar gating memristor and a bipolar gating memristor. The preparation method includes: preparing a lower electrode; depositing a resistive material layer on the lower electrode; and depositing an upper electrode on the resistive material layer by using a magnetron sputtering manner to deposit the upper electrode, controlling upper electrode metal particles to have suitable kinetic energy by controlling sputtering power, controlling a vacuum degree of a region where the upper electrode and the resistive material layer are located, such that a redox reaction occurs spontaneously between the upper electrode and the resistive material layer during the deposition of the upper electrode to form a built-in bipolar gating layer; and continuously depositing the upper electrode on the built-in bipolar gating layer.