公开(公告)号：US12135900B2

公开(公告)日：2024-11-05

申请号：US17500901

申请日：2021-10-13

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang ,  Xu Hui Cheng ,  Wan-Jun Hong

IPC: G06F3/06

Abstract: A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.

公开(公告)号：US11822798B2

公开(公告)日：2023-11-21

申请号：US17555487

申请日：2021-12-19

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.

公开(公告)号：US11693567B2

公开(公告)日：2023-07-04

申请号：US17533020

申请日：2021-11-22

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang ,  Xu Hui Cheng ,  Dong Sheng Rao

IPC: G06F3/06 ,  G06F1/3287 ,  G06F13/16 ,  G06F1/3234

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/1668

Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

公开(公告)号：US20230205451A1

公开(公告)日：2023-06-29

申请号：US17579537

申请日：2022-01-19

Applicant: Hefei Core Storage Electronic Limited

Inventor： Wan-Jun Hong ,  Qi-Ao Zhu ,  Xin Wang ,  Yang Zhang ,  Xu Hui Cheng ,  Jian Hu

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.

公开(公告)号：US11669270B1

公开(公告)日：2023-06-06

申请号：US17579537

申请日：2022-01-19

Applicant: Hefei Core Storage Electronic Limited

Inventor： Wan-Jun Hong ,  Qi-Ao Zhu ,  Xin Wang ,  Yang Zhang ,  Xu Hui Cheng ,  Jian Hu

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.

公开(公告)号：US20230098366A1

公开(公告)日：2023-03-30

申请号：US17500901

申请日：2021-10-13

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang ,  Xu Hui Cheng ,  Wan-Jun Hong

IPC: G06F3/06

Abstract: A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.

公开(公告)号：US20240295982A1

公开(公告)日：2024-09-05

申请号：US18298345

申请日：2023-04-10

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Wan-Jun Hong ,  Qi-Ao Zhu ,  Yang Zhang ,  Xin Wang

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory operation control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. Management data is established, which includes status recording data. First status information corresponding to a first physical unit is stored in the status recording data. An operation command is received from a host system. The management data is queried according to the operation command. Whether to allow an execution of the operation command on the first physical unit is determined according to a query result.

公开(公告)号：US20230161489A1

公开(公告)日：2023-05-25

申请号：US17555487

申请日：2021-12-19

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.

公开(公告)号：US20230127512A1

公开(公告)日：2023-04-27

申请号：US17533020

申请日：2021-11-22

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang ,  Xu Hui Cheng ,  Dong Sheng Rao

IPC: G06F3/06 ,  G06F13/16 ,  G06F1/3234 ,  G06F1/3287

Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

公开(公告)号：US11221791B2

公开(公告)日：2022-01-11

申请号：US16547598

申请日：2019-08-22

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Xin Wang ,  Kai-Di Zhu

IPC: G06F3/06

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a first write command from a host system; instructing a rewritable non-volatile memory module to perform a first write operation according to the first write command; obtaining first performance information corresponding to the first write operation; and updating threshold information according to the first performance information, wherein the threshold information is configured to determine a type of target data.