公开(公告)号：US11954020B2

公开(公告)日：2024-04-09

申请号：US17740268

申请日：2022-05-09

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Qi-Ao Zhu ,  Xu Hui Cheng

IPC: G06F12/02 ,  G06F1/20

CPC classification number: G06F12/0238 ,  G06F1/206 ,  G06F2212/2022

Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.

公开(公告)号：US20230325310A1

公开(公告)日：2023-10-12

申请号：US17740268

申请日：2022-05-09

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Qi-Ao Zhu ,  Xu Hui Cheng

IPC: G06F12/02 ,  G06F1/20

CPC classification number: G06F12/0238 ,  G06F1/206 ,  G06F2212/2022

Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. The method includes: determining whether a first temperature value is greater than a first threshold value; in response to determining that the first temperature value is greater than the first threshold value, performing a speed-down operation to reduce an access speed of a memory storage device to a first speed; when the memory storage device performs data access at the first speed, determining whether a second temperature value is less than a second threshold value; in response to determining that the second temperature value is less than the second threshold value, calculating a first temperature change rate within a specific time range, and determining a first adjustment percentage according to the first temperature change rate; and calculating a second speed according to the first speed and the first adjustment percentage, and adjusting the access speed of the memory storage device to the second speed.

公开(公告)号：US20230127512A1

公开(公告)日：2023-04-27

申请号：US17533020

申请日：2021-11-22

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang ,  Xu Hui Cheng ,  Dong Sheng Rao

IPC: G06F3/06 ,  G06F13/16 ,  G06F1/3234 ,  G06F1/3287

Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

公开(公告)号：US11175847B2

公开(公告)日：2021-11-16

申请号：US16822023

申请日：2020-03-18

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Wan-Jun Hong ,  Jing Zhang ,  Xin Wang ,  Xu Hui Cheng

IPC: G06F3/06 ,  G06F12/02

Abstract: A data merging method for flash memory, a flash memory control circuit unit and a flash memory storage device are provided. The disclosure is applicable to a flash memory, an embedded memory device or a solid state drive of 3D structure. The method includes: selecting at least one source physical erasing unit from at least one first physical erasing unit according to a valid data count of the at least one first physical erasing unit and a valid data count of each of a plurality of memory sub-modules; and copying valid data in the at least one source physical erasing unit to at least one destination physical erasing unit to perform a valid data merging operation.

公开(公告)号：US20210223976A1

公开(公告)日：2021-07-22

申请号：US16822023

申请日：2020-03-18

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Wan-Jun Hong ,  Jing Zhang ,  Xin Wang ,  Xu Hui Cheng

IPC: G06F3/06

Abstract: A data merging method for flash memory, a flash memory control circuit unit and a flash memory storage device are provided. The disclosure is applicable to a flash memory, an embedded memory device or a solid state drive of 3D structure. The method includes: selecting at least one source physical erasing unit from at least one first physical erasing unit according to a valid data count of the at least one first physical erasing unit and a valid data count of each of a plurality of memory sub-modules; and copying valid data in the at least one source physical erasing unit to at least one destination physical erasing unit to perform a valid data merging operation.

公开(公告)号：US12135900B2

公开(公告)日：2024-11-05

申请号：US17500901

申请日：2021-10-13

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang ,  Xu Hui Cheng ,  Wan-Jun Hong

IPC: G06F3/06

Abstract: A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.

公开(公告)号：US11693567B2

公开(公告)日：2023-07-04

申请号：US17533020

申请日：2021-11-22

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang ,  Xu Hui Cheng ,  Dong Sheng Rao

IPC: G06F3/06 ,  G06F1/3287 ,  G06F13/16 ,  G06F1/3234

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/1668

Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

公开(公告)号：US20230205451A1

公开(公告)日：2023-06-29

申请号：US17579537

申请日：2022-01-19

Applicant: Hefei Core Storage Electronic Limited

Inventor： Wan-Jun Hong ,  Qi-Ao Zhu ,  Xin Wang ,  Yang Zhang ,  Xu Hui Cheng ,  Jian Hu

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.

公开(公告)号：US11669270B1

公开(公告)日：2023-06-06

申请号：US17579537

申请日：2022-01-19

Applicant: Hefei Core Storage Electronic Limited

Inventor： Wan-Jun Hong ,  Qi-Ao Zhu ,  Xin Wang ,  Yang Zhang ,  Xu Hui Cheng ,  Jian Hu

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.

公开(公告)号：US20230098366A1

公开(公告)日：2023-03-30

申请号：US17500901

申请日：2021-10-13

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang ,  Xu Hui Cheng ,  Wan-Jun Hong

IPC: G06F3/06

Abstract: A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.