公开(公告)号：US11714755B2

公开(公告)日：2023-08-01

申请号：US16944905

申请日：2020-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Schumacher ,  Randy Passint ,  Thomas McGee ,  Michael Malewicki ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F13/40 ,  G06F12/0815

CPC classification number: G06F12/0815 ,  G06F13/4027 ,  G06F2212/1032

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

公开(公告)号：US11586541B2

公开(公告)日：2023-02-21

申请号：US16944905

申请日：2020-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Schumacher ,  Randy Passint ,  Thomas McGee ,  Michael Malewicki ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F13/40 ,  G06F12/0815

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

公开(公告)号：US11573898B2

公开(公告)日：2023-02-07

申请号：US16995411

申请日：2020-08-17

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Randy Passint ,  Paul Frank ,  Russell L. Nicol ,  Thomas McGee ,  Michael Woodacre

IPC: G06F12/0831 ,  G06F13/40

Abstract: A node controller is provided to include a first interface to interface with one or more processors, a second interface including a plurality of ports to interface with node controllers within a base node and other nodes in the cache-coherent interconnect network. The node controller can further include a third interface to interface with a first plurality of memory devices and a cache coherence management logic. The cache coherence management logic can maintain, based on a first circuitry, hardware-managed cache coherency in the cache-coherent interconnect network. The cache coherence management logic can further facilitate, based on a second circuitry, software-managed cache coherency in the cache-coherent interconnect network.

公开(公告)号：US20220035742A1

公开(公告)日：2022-02-03

申请号：US16944905

申请日：2020-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Schumacher ,  Randy Passint ,  Thomas McGee ,  Michael Malewicki ,  Michael S. Woodacre

IPC: G06F12/0815 ,  G06F13/40

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.