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公开(公告)号：US11976984B1
公开(公告)日：2024-05-07
申请号：US18182339
申请日：2023-03-12
Inventor： Zhiqiang Wang , Yayong Yang , Guoqing Xin , Xiaojie Shi , Yong Kang
CPC classification number: G01K7/22 , G01K15/005
Abstract: The present disclosure belongs to the technical field of power electronic converters, and discloses a method and a system for predicting a junction temperature of a power semiconductor module in the full life cycle and a terminal. The method includes the steps: arranging an NTC thermistor network to monitor the temperature of each area inside the power module when the power module works; obtaining data for training the neural network by utilizing finite element simulation or experiments, and building a neural network model among the temperature of the NTC resistor network, a water flow rate, an aging factor and the junction temperature of the chip under working conditions. The present disclosure improves the junction temperature prediction accuracy of areas with relatively large errors comprehensively and realizes the high-precision junction temperature prediction under all working conditions.
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Patent Agency Ranking
公开(公告)号：US12178022B2
公开(公告)日：2024-12-24
申请号：US18190751
申请日：2023-03-27
Inventor： Zhiqiang Wang , Yu Liao , Guoqing Xin , Xiaojie Shi , Yong Kang
IPC: H05K7/20
Abstract: The present disclosure relates to the technical field of heat dissipation for electronic devices, and discloses a manifold microchannel heat sink based on directional optimization of hotspot areas, including a power module, a heat dissipation substrate, a cold source device, and a diverter manifold; the heat dissipation substrate is arranged on the power module, a microchannel is provided on a side of the heat dissipation substrate away from the power module and on a back of a heat generating area of the power module for carrying the power module and dissipating heat from the power module. According to the manifold microchannel heat sink based on the directional optimization of hotspot areas, the local heat dissipation performance of the power module may be preliminarily changed by optimizing the microchannel on the heat dissipation substrate, which avoids poor heat dissipation temperature uniformity in a multi-heat source system.
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公开(公告)号：US10943845B2
公开(公告)日：2021-03-09
申请号：US16430599
申请日：2019-06-04
Inventor： Cai Chen , Zhizhao Huang , Yuxiong Li , Yu Chen , Yong Kang
IPC: H01L23/36 , H01L25/16 , H01L23/538 , H05K1/02 , H05K1/11 , H05K3/34 , H05K3/06 , H01L25/07 , H05K1/14 , H01L23/373 , H05K1/09 , H05K1/18 , H01L23/467
Abstract: A three-dimensional packaging structure and a packaging method of power devices. The packaging structure includes power devices, direct copper bonded substrates (i.e., DBC substrates), flexible printed circuit boards (i.e., FPC boards), bonding wires, heat dissipation substrates, decoupling capacitors, a heatsink with integrating the fan, shells, and forms a half-bridge circuit structure composed by the power devices. The power circuit structure is optimized, parasitic inductance in the commutation loop is reduced by mutual inductance cancellation, thus overvoltage and oscillation during the power device switching process can be reduced. Additionally, by using the flexible characteristic of the flexible PCB, a three-dimensional packaging structure is formed and power density is improved.
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公开(公告)号：US20220099731A1
公开(公告)日：2022-03-31
申请号：US17483411
申请日：2021-09-23
Abstract: An evaluation module configured to evaluate the lifespan of a multichip module, the multichip module comprising a first substrate and multiple chips under evaluation, includes a second substrate, configured to be the same as the first substrate, and having attachment positions corresponding to the attachment positions on the first substrate, and at least one evaluation chip, configured to be the same as the multiple chips under evaluation. The number of evaluation chips is less than the number of chips under evaluation by at least one. The at least one evaluation chip is arranged at an attachment position on the second substrate, such that the at least one evaluation chip and the chip under evaluation arranged at the corresponding attachment position on the multichip module have the same cooling performance and sustain the same thermal stress. The present disclosure also discloses a method for evaluating the lifespan of a multichip module.
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公开(公告)号：US10354937B2
公开(公告)日：2019-07-16
申请号：US15843415
申请日：2017-12-15
Inventor： Cai Chen , Zhizhao Huang , Yuxiong Li , Yu Chen , Yong Kang
IPC: H05K3/34 , H01L23/46 , H01L23/36 , H01L25/16 , H05K1/02 , H05K1/09 , H05K1/14 , H05K1/11 , H05K3/06 , H05K1/18 , H01L23/373 , H01L23/538 , H01L23/467
Abstract: A three-dimensional packaging structure and a packaging method of power devices. The packaging structure includes power devices, direct copper bonded substrates (i.e., DBC substrates), flexible printed circuit boards (i.e., FPC boards), bonding wires, heat dissipation substrates, decoupling capacitors, a heatsink with integrating the fan, shells, and forms a half-bridge circuit structure composed by the power devices. The power circuit structure is optimized, parasitic inductance in the commutation loop is reduced by mutual inductance cancellation, thus overvoltage and oscillation during the power device switching process can be reduced. Additionally, by using the flexible characteristic of the flexible PCB, a three-dimensional packaging structure is formed and power density is improved.
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公开(公告)号：US12111348B2
公开(公告)日：2024-10-08
申请号：US17483411
申请日：2021-09-23
CPC classification number: G01R31/2874 , H01L25/115 , H01L29/1608
Abstract: An evaluation module configured to evaluate the lifespan of a multichip module, the multichip module comprising a first substrate and multiple chips under evaluation, includes a second substrate, configured to be the same as the first substrate, and having attachment positions corresponding to the attachment positions on the first substrate, and at least one evaluation chip, configured to be the same as the multiple chips under evaluation. The number of evaluation chips is less than the number of chips under evaluation by at least one. The at least one evaluation chip is arranged at an attachment position on the second substrate, such that the at least one evaluation chip and the chip under evaluation arranged at the corresponding attachment position on the multichip module have the same cooling performance and sustain the same thermal stress. The present disclosure also discloses a method for evaluating the lifespan of a multichip module.
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