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    APPARATUS AND METHOD FOR PROVIDING AUGMENTED REALITY INFORMATION
    1.
    发明申请
    APPARATUS AND METHOD FOR PROVIDING AUGMENTED REALITY INFORMATION 审中-公开
    用于提供已实现的现实信息的装置和方法

    公开(公告)号：US20120038670A1

    公开(公告)日：2012-02-16

    申请号：US13168210

    申请日：2011-06-24

    Applicant: Jung-Hak CHOI ,  Kyu-Tae KIM ,  Hye-Jin KIM ,  Young-Jin OH ,  Nam-Young RYU ,  Man-Jung YI ,  Woo-Yean JEONG

    Inventor： Jung-Hak CHOI ,  Kyu-Tae KIM ,  Hye-Jin KIM ,  Young-Jin OH ,  Nam-Young RYU ,  Man-Jung YI ,  Woo-Yean JEONG

    IPC: G09G5/00

    CPC classification number: G06T19/006 ,  G06T7/70

    Abstract: An apparatus, system, and method for providing augmented reality (AR) information of a concealed object are disclosed. The method for providing AR information of a concealed object by a terminal connectable to a server via a wired and/or wireless communication network may include acquiring an image of a real environment; defining a reference object included in the acquired image; obtaining image capturing position information about a position of the image and reference object recognition information of the defined reference object; transmitting the obtained image capturing position information and the reference object recognition information to the server; receiving information about concealed objects from the server, the concealed objects being disposed behind the reference object along or about a direction from the image capturing position to the reference object; and outputting the received information about concealed objects.

    Abstract translation: 公开了一种用于提供隐藏对象的增强现实（AR）信息的装置，系统和方法。 通过有线和/或无线通信网络可连接到服务器的终端提供隐藏对象的AR信息的方法可以包括获取真实环境的图像; 定义包括在所获取的图像中的参考对象; 获取关于图像的位置和所定义的参考对象的参考对象识别信息的图像捕获位置信息; 将获得的图像拍摄位置信息和参考对象识别信息发送到服务器; 从所述服务器接收关于隐藏对象的信息，所述隐藏对象沿着或围绕从所述图像拍摄位置到所述参考对象的方向设置在所述参考对象之后; 并输出所接收的关于隐藏对象的信息。

    PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS
    2.
    发明申请
    PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS 有权
    相变存储器件和系统以及相关编程方法

    公开(公告)号：US20100008133A1

    公开(公告)日：2010-01-14

    申请号：US12559792

    申请日：2009-09-15

    Applicant: Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

    Inventor： Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

    IPC: G11C11/00 ,  G11C7/10 ,  G11C7/06 ,  G11C7/00

    CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

    Abstract: A method of writing data in a phase change memory includes; receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is equal to the write data, and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications.

    Abstract translation: 在相变存储器中写入数据的方法包括： 接收要写入所述多个相变存储单元中的所选择的相变存储单元的写入数据，感测存储在所选择的相变存储单元中的数据，确定所感测的数据是否等于写入数据，以及如果 感测数据不等于写数据，对所选择的相变存储单元迭代地施加写入电流，其中相变存储单元的电阻状态根据与写入电流的电平相对应的热量而改变， 写入电流在连续的迭代应用程序之间改变。

    PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS
    3.
    发明申请
    PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS 有权
    相变存储器件和系统以及相关编程方法

    公开(公告)号：US20090161421A1

    公开(公告)日：2009-06-25

    申请号：US12395999

    申请日：2009-03-02

    Applicant: Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

    Inventor： Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

    IPC: G11C11/00 ,  G11C11/416

    CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

    Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

    Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。

    PIEZOELECTRIC SPEAKER
    4.
    发明申请
    PIEZOELECTRIC SPEAKER 有权
    压电扬声器

    公开(公告)号：US20120148073A1

    公开(公告)日：2012-06-14

    申请号：US13289225

    申请日：2011-11-04

    Applicant: Hye-Jin KIM ,  Woo Seok Yang ,  Jongdae Kim

    Inventor： Hye-Jin KIM ,  Woo Seok Yang ,  Jongdae Kim

    IPC: H04R17/00

    CPC classification number: H04R17/005 ,  H04R2201/003 ,  H04R2307/025 ,  H04R2499/15

    Abstract: Disclosed is a piezoelectric speaker including: a piezoelectric layer that converts electrical signals into oscillation and outputs sound; an electrode that is formed on a top or a bottom of the piezoelectric layer to apply the electrical signals to the piezoelectric layer; an acoustic diaphragm that is made of a hetero material including a first acoustic diaphragm and a second acoustic diaphragm and is attached to the bottom of the piezoelectric layer on which the electrode is formed; and a frame attached in a form enclosing a side of the acoustic diaphragm.

    Abstract translation: 公开了一种压电扬声器，包括：将电信号转换为振荡并输出声音的压电层; 形成在压电层的顶部或底部上以将电信号施加到压电层的电极; 由包括第一声膜和第二声膜的异质材料制成并且附着在其上形成有电极的压电层的底部的声膜; 以及以包围隔膜的一侧的形式附接的框架。

    HUMIDITY SENSOR HAVING ANODIC ALUMINUM OXIDE LAYER, AND FABRICATING METHOD THEREOF
    5.
    发明申请
    HUMIDITY SENSOR HAVING ANODIC ALUMINUM OXIDE LAYER, AND FABRICATING METHOD THEREOF 有权
    具有阳极氧化铝层的湿度传感器及其制造方法

    公开(公告)号：US20100134948A1

    公开(公告)日：2010-06-03

    申请号：US12617848

    申请日：2009-11-13

    Applicant: Hyun-Chul PARK ,  Hye-Jin KIM ,  Woon-Bong HWANG ,  Young-Deuk KIM ,  Kun-Hong LEE

    Inventor： Hyun-Chul PARK ,  Hye-Jin KIM ,  Woon-Bong HWANG ,  Young-Deuk KIM ,  Kun-Hong LEE

    IPC: H01G5/012 ,  B05D5/12 ,  G03F7/20

    CPC classification number: G01N27/223

    Abstract: Disclosed are a humidity sensor and a fabricating method thereof. The humidity sensor includes a substrate, an anodic aluminum oxide layer formed on the substrate and having a plurality of holes, and electrodes formed on the anodic aluminum oxide layer, in order to improve sensitivity and accuracy of the humidity sensor. Further, the fabricating method of a humidity sensor includes preparing an aluminum substrate, forming an anodic aluminum oxide layer by oxidizing the aluminum substrate, and forming electrodes on the anodic aluminum oxide layer.

    Abstract translation: 公开了一种湿度传感器及其制造方法。 为了提高湿度传感器的灵敏度和精度，湿度传感器包括基板，形成在基板上并具有多个孔的阳极氧化铝层和形成在阳极氧化铝层上的电极。 此外，湿度传感器的制造方法包括制备铝基板，通过氧化铝基板形成阳极氧化铝层，以及在阳极氧化铝层上形成电极。

    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE MATERIALS
    7.
    发明申请
    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE MATERIALS 审中-公开
    使用可变电阻材料的非易失性存储器件

    公开(公告)号：US20080291715A1

    公开(公告)日：2008-11-27

    申请号：US12116295

    申请日：2008-05-07

    Applicant: Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

    Inventor： Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/0038 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

    Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and supplying the nonvolatile memory cell a read bias based on the control bias. The control bias generating circuit receives an input bias, generates the control bias based on the input bias and supplies the control bias to the read circuit. A slope of the control bias to the input bias is less than 1.

    Abstract translation: 非易失性存储器件包括非易失性存储单元，读取电路和控制偏置产生电路。 非易失性存储单元具有根据存储的数据而改变的电阻水平。 读取电路通过接收控制偏置来读取非易失性存储单元的电阻电平，并且基于控制偏压向非易失性存储单元提供读取偏置。 控制偏置产生电路接收输入偏置，基于输入偏置产生控制偏压，并将控制偏压提供给读取电路。 对输入偏置的控制偏置的斜率小于1。

    BIAS VOLTAGE GENERATOR AND METHOD GENERATING BIAS VOLTAGE FOR SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    BIAS VOLTAGE GENERATOR AND METHOD GENERATING BIAS VOLTAGE FOR SEMICONDUCTOR MEMORY DEVICE 有权
    偏置电压发生器和生成半导体存储器件的偏置电压的方法

    公开(公告)号：US20080159017A1

    公开(公告)日：2008-07-03

    申请号：US11955562

    申请日：2007-12-13

    Applicant: Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

    Inventor： Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

    IPC: G11C5/14

    CPC classification number: G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

    Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。

    SEMICONDUCTOR MEMORY DEVICE HAVING RESISTIVE MEMORY CELLS AND METHOD OF TESTING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING RESISTIVE MEMORY CELLS AND METHOD OF TESTING THE SAME 有权
    具有电阻记忆体的半导体存储器件及其测试方法

    公开(公告)号：US20140022836A1

    公开(公告)日：2014-01-23

    申请号：US13945007

    申请日：2013-07-18

    Applicant: Hye-Jin KIM ,  Hyung-Rok OH ,  Dong-Seok KANG ,  Dong-Hyun SOHN ,  Sang-Beom KANG ,  Chul-Woo PARK ,  Yun-Sang LEE

    Inventor： Hye-Jin KIM ,  Hyung-Rok OH ,  Dong-Seok KANG ,  Dong-Hyun SOHN ,  Sang-Beom KANG ,  Chul-Woo PARK ,  Yun-Sang LEE

    IPC: G11C29/10 ,  G11C11/16

    CPC classification number: G11C29/10 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/32 ,  G11C29/34 ,  G11C2029/2602

    Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. The MTJ element includes a free layer, a barrier layer and a pinned layer. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

    Abstract translation: 半导体存储器件包括存储单元阵列，模式寄存器组和测试电路。 存储单元阵列包括多个字线，多个位线和多个自旋转移转矩磁阻随机存取存储器（STT-MRAM）单元，每个STT-MRAM单元设置在每个字线的交叉区域 和位线，并且STT-MRAM单元包括磁隧道结（MTJ）元件和单元晶体管。 MTJ元件包括自由层，阻挡层和钉扎层。 单元晶体管的栅极耦合到字线，单元晶体管的第一电极通过MTJ元件耦合到位线，并且单元晶体管的第二电极耦合到源极线。 模式寄存器组被配置为设置测试模式，并且测试电路被配置为通过使用模式寄存器集执行测试操作。

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