公开(公告)号：US10763159B2

公开(公告)日：2020-09-01

申请号：US16518361

申请日：2019-07-22

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Christopher Wilson ,  Juergen Boemmels

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522

Abstract: A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level.

公开(公告)号：US20210193512A1

公开(公告)日：2021-06-24

申请号：US17081337

申请日：2020-10-27

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Zsolt Tokei ,  Christopher Wilson ,  Stefan Decoster

IPC: H01L21/768 ,  H01L23/538 ,  H01L21/033

Abstract: A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.

公开(公告)号：US10242907B2

公开(公告)日：2019-03-26

申请号：US15615299

申请日：2017-06-06

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Juergen Boemmels ,  Christopher Wilson

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528

Abstract: A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the hard mask layer with a set of parallel material lines delimiting gaps therebetween; and (c) providing a spacer layer following the shape of the material layer. The method further includes (d) removing a top portion of the spacer layer, thereby forming spacer lines alternatively separated by material lines and by gaps; and (e) providing a blocking element in a portion of a gap. The method also includes (f) etching selectively the hard mask layer by using the material layer, the spacer lines and the blocking element as a mask, thereby providing a first set of parallel trenches in the hardmask layer, wherein a trench has a blocked portion; and (g) selectively removing the blocking element.

公开(公告)号：US20170256451A1

公开(公告)日：2017-09-07

申请号：US15451175

申请日：2017-03-06

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure and a method for forming it is disclosed. In one aspect, the method includes the steps of providing a first entity. The first entity includes a first set of line structures. The first set of line structures include a first set of conductive lines, and a first set of dielectric lines made of a first dielectric material and aligned with and overlaying the first set of conductive lines. The first entity also includes gaps separating the line structures and filled with a second dielectric material of such a nature that the first dielectric material can be selectively etched with respect to the second dielectric material. The method also includes providing a patterned mask on the first entity. The method further includes etching selectively the first dielectric material through the patterned mask so as to form one or more vias in the first dielectric material. The method also includes removing the patterned mask.

公开(公告)号：US11270912B2

公开(公告)日：2022-03-08

申请号：US17110631

申请日：2020-12-03

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Christopher Wilson ,  Zsolt Tokei ,  Ryan Ryoung han Kim

IPC: H01L21/768

Abstract: Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.

公开(公告)号：US20210183698A1

公开(公告)日：2021-06-17

申请号：US17110631

申请日：2020-12-03

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Christopher Wilson ,  Zsolt Tokei ,  Ryan Ryoung han Kim

IPC: H01L21/768

Abstract: Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.

公开(公告)号：US10395978B2

公开(公告)日：2019-08-27

申请号：US15907118

申请日：2018-02-27

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Farid Sebaai ,  Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson ,  Katia Devriendt

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/308

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.

公开(公告)号：US20180247863A1

公开(公告)日：2018-08-30

申请号：US15907118

申请日：2018-02-27

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Farid Sebaai ,  Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson ,  Katia Devriendt

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.

公开(公告)号：US09859161B2

公开(公告)日：2018-01-02

申请号：US15451175

申请日：2017-03-06

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure and a method for forming it is disclosed. In one aspect, the method includes the steps of providing a first entity. The first entity includes a first set of line structures. The first set of line structures include a first set of conductive lines, and a first set of dielectric lines made of a first dielectric material and aligned with and overlaying the first set of conductive lines. The first entity also includes gaps separating the line structures and filled with a second dielectric material of such a nature that the first dielectric material can be selectively etched with respect to the second dielectric material. The method also includes providing a patterned mask on the first entity. The method further includes etching selectively the first dielectric material through the patterned mask so as to form one or more vias in the first dielectric material. The method also includes removing the patterned mask.

公开(公告)号：US11264271B2

公开(公告)日：2022-03-01

申请号：US17081337

申请日：2020-10-27

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Zsolt Tokei ,  Christopher Wilson ,  Stefan Decoster

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/538

Abstract: A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.