公开(公告)号：US20230382758A1

公开(公告)日：2023-11-30

申请号：US18325823

申请日：2023-05-30

Applicant: IMEC VZW

Inventor： Michiel Jan van Setten ,  Geoffrey Pourtois ,  Hendrik F.W. Dekkers ,  Gouri Sankar Kar

IPC: C01G30/00 ,  H01L29/786

CPC classification number: C01G30/005 ,  H01L29/78693 ,  C01P2002/02

Abstract: Mixed metal oxides and methods for making the mixed metal oxides are disclosed. A mixed metal oxide includes metal or metalloid elements including 0.50 to 0.90 parts by mole Mg, 0.05 to 0.30 parts by mole Al, 0.01 to 0.20 parts by mole Sb, and 0.00 to 0.31 parts by mole of other elements selected from metals and metalloids. The sum of all parts by mole of Mg, Al, Sb, and the other elements selected from metals and metalloids may amount to about 1.00. The mixed metal oxide additionally includes oxygen, and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.

公开(公告)号：US20190221610A1

公开(公告)日：2019-07-18

申请号：US16234381

申请日：2018-12-27

Applicant: IMEC vzw

Inventor： Romain Delhougne ,  Davide Francesco Crotti ,  Gouri Sankar Kar ,  Luca Di Piazza ,  Ludovic Goux

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/11597

CPC classification number: H01L27/249 ,  H01L27/11597 ,  H01L27/2409 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1683

Abstract: In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.

公开(公告)号：US20170179378A1

公开(公告)日：2017-06-22

申请号：US15387127

申请日：2016-12-21

Applicant: IMEC VZW

Inventor： Gouri Sankar Kar ,  Jürgen Bömmels ,  Davide Crotti

IPC: H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices having an integrated magnetic tunnel junction (MTJ), and relates to methods of fabricating the semiconductor devices. In one aspect, a semiconductor device includes a stack including successive layers of: a first metallization layer, a first dielectric layer, a second metallization layer, a second dielectric layer, and a third metallization layer. A magnetic tunnel junction (MTJ) device is formed in the first dielectric layer and in the second metallization layer and electrically connected to a first metallization layer and the third metallization layer.

公开(公告)号：US11910725B2

公开(公告)日：2024-02-20

申请号：US17121279

申请日：2020-12-14

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Bart Vermeulen ,  Mihaela Ioana Popovici ,  Koen Martens ,  Gouri Sankar Kar

IPC: H10N50/85 ,  H01F10/32 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/85 ,  H01F10/3286 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: The present disclosure relates to magnetic devices. In particular, the disclosure relates to magnetic memory and logic devices that employ the voltage control of magnetic anisotropy (VCMA) effect for magnetization switching. The present disclosure provides a method for manufacturing a magnetic structure for such a magnetic device. The method comprising the following steps: providing a bottom electrode layer, forming a SrTiO3 (STO) stack on the bottom electrode layer by atomic layer deposition (ALD) of at least two different STO nanolaminates, forming a magnetic layer on the STO stack, and forming a perpendicular magnetic anisotropy (PMA) promoting layer on the magnetic layer, the PMA promoting layer being configured to promote PMA in the magnetic layer.

公开(公告)号：US20220076383A1

公开(公告)日：2022-03-10

申请号：US17366350

申请日：2021-07-02

Applicant: IMEC VZW

Inventor： Bappaditya Dey ,  Sandip Halder ,  Gouri Sankar Kar ,  Victor M. Blanco ,  Senthil Srinivasan Shanmugam Vadakupudhu Palayam

IPC: G06T5/00

Abstract: The disclosure relates generally to image processing. For example, the invention relates to a method and a device for de-noising an electron microscope (EM) image. The method includes the act of selecting a patch of the EM image, wherein the patch comprises a plurality of pixels, wherein the following acts are performed on the patch: i) replacing the value of one pixel, for example of a center pixel, of the patch with the value of a different, for example randomly selected, pixel from the same EM image; ii) determining a de-noised value for the one pixel based on the values of the other pixels in the patch; and iii) replacing the value of the one pixel with the determined de-noised value.

公开(公告)号：US11165013B2

公开(公告)日：2021-11-02

申请号：US16720517

申请日：2019-12-19

Applicant: IMEC vzw

Inventor： Kevin Garello ,  Gouri Sankar Kar

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: The disclosed technology generally relates to magnetic devices and more particularly to magnetic tunnel junction (MTJ) devices in which switching can be mediated by spin-orbit torque, and further relates to a method of fabricating such devices. In an aspect, a magnetic tunnel junction (MTJ) device includes a spin-orbit torque (SOT) mediating layer, a hard-mask layer used to define a shape of the SOT layer, a magnetic tunnel junction arranged between the SOT layer and the hard-mask layer. The MTJ includes at least a free layer and a reference layer separated by a non-magnetic barrier layer. The device further includes at least two electrical accesses arranged to contact the SOT layer to pass a write current therethrough. To provide field-free switching of the free layer, the device further includes a ferromagnetic element as at least one of a ferromagnetic sublayer of the hard-mask and a material in the electrical accesses.

公开(公告)号：US11075261B2

公开(公告)日：2021-07-27

申请号：US16677309

申请日：2019-11-07

Applicant: IMEC vzw

Inventor： Mihaela Ioana Popovici ,  Ludovic Goux ,  Gouri Sankar Kar

IPC: H01L49/02 ,  H01L27/108 ,  H01L21/02 ,  H01L21/285

Abstract: The disclosed technology relates to a structure for use in a metal-insulator-metal capacitor. In one aspect, the structure comprises a bottom electrode formed of a Ru layer. The Ru layer has a top surface characterized by a grazing incidence X-ray diffraction spectrum comprising a first intensity and a second intensity, the first intensity corresponding to a diffracting plane of Miller indices (0 0 2) being larger than the second intensity corresponding to a diffracting plane of Miller indices (1 0 1). The structure further comprises an interlayer on the top surface of the Ru layer, the interlayer being formed of an oxide of Sr and Ru having a cubic lattice structure, and a dielectric layer on the interlayer, the dielectric layer being formed of an oxide of Sr and Ti.

公开(公告)号：US20190221608A1

公开(公告)日：2019-07-18

申请号：US16236051

申请日：2018-12-28

Applicant: IMEC vzw

Inventor： Gouri Sankar Kar ,  Stefan Cosemans

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A magnetic tunnel junction memory device is disclosed. In one aspect, the memory device comprises a substrate, a first memory element, and a second memory element, wherein the first memory element and the second memory element are formed of a stack comprising at least a first layer and a second layer, the first layer being arranged between the substrate and the second layer. The memory device further comprises a first selector device arranged to contact the first memory element, and a second selector device arranged to contact the second memory element, wherein the first selector device and the second selector device are arranged in or above the second layer. The first memory element and the second memory element are interconnected via the first layer, and are separated from each other by a trench formed in the second layer.

公开(公告)号：US20240107739A1

公开(公告)日：2024-03-28

申请号：US18472122

申请日：2023-09-21

Applicant: IMEC VZW

Inventor： Nouredine Rassoul ,  Hyungrock Oh ,  Romain Delhougne ,  Gouri Sankar Kar ,  Attilio Belmonte ,  Kaustuv Banerjee ,  Mohit Gupta

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A memory device configured as a dynamic random access memory is provided, comprising a first semiconductor device layer comprising a first bit cell and a second semiconductor device layer comprising a second DRAM bit cell. Further, at least one of a first and second interconnecting structure is provided, the first interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a write word line common to the gate terminal of the write transistors of the first and second bit cells, and the second interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a read word line common to a first source/drain terminal of the read transistors of the first and second bit cells.

公开(公告)号：US20230200078A1

公开(公告)日：2023-06-22

申请号：US18065335

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Mihaela Ioana Popovici ,  Jan Van Houdt ,  Amey Mahadev Walke ,  Gouri Sankar Kar ,  Jasper Bizindavyi

IPC: H10B51/00 ,  H01L29/786 ,  H01L27/12 ,  C23C16/455

CPC classification number: H01L27/11585 ,  C23C16/45536 ,  H01L27/1222 ,  H01L28/60 ,  H01L29/7869

Abstract: Example embodiments relate to ferroelectric devices. An example ferroelectric device layer structure includes a first electrode. The ferroelectric device layer structure also includes a second electrode. Additionally, the ferroelectric device layer structure includes a ferroelectric layer of hafnium zirconate (HZO). Further, the ferroelectric device layer structure includes an oxide layer of Nb2O5 or Ta2O5 arranged on the ferroelectric layer. The ferroelectric layer and the oxide layer are arranged between the first electrode and the second electrode.