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1.发明授权Method for operating field-effect transistor, field-effect transistor and circuit configuration 有权操作场效应晶体管，场效应晶体管和电路配置的方法公开(公告)号：US09184284B2
公开(公告)日：2015-11-10
申请号：US13731422
申请日：2012-12-31
Applicant: Infineon Technologies AG
Inventor： Markus Zundel , Peter Nelle
CPC classification number: H01L29/7827 , H01L29/407 , H01L29/41766 , H01L29/7804 , H01L29/7813 , H03K17/145 , H03K17/162
Abstract: A method for operating a field-effect transistor having a source terminal, a drain terminal, a gate terminal, a drift region and a dielectric region adjoining the drift region, is provided. The method includes: connecting at least one of the drain terminal and the source terminal to a load; applying a sequence of voltage pulses between the gate terminal and the source terminal to repetitively switch the field-effect transistor such that the field-effect transistor is driven in an avalanche mode between the voltage pulses, during the avalanche mode avalanche multiplication occurring in the drift region close to the dielectric region; and applying at least one relaxation pulse to the field-effect transistor to reduce an accumulation of charges in the dielectric region due to hot charge carriers generated in the avalanche mode. Further, a field-effect transistor and a circuit configuration including the field-effect transistor are provided.
Abstract translation: 提供一种用于操作具有源极端子，漏极端子，栅极端子，漂移区域和与漂移区域相邻的电介质区域的场效应晶体管的方法。 该方法包括：将至少一个漏极端子和源极端子连接到负载; 在栅极端子和源极端子之间施加一系列电压脉冲以重复地切换场效应晶体管，使得场效应晶体管在电压脉冲之间以雪崩模式驱动，在雪崩模式中，在漂移中出现雪崩倍增 靠近电介质区域的区域; 以及向场效应晶体管施加至少一个弛豫脉冲，以减少由于在雪崩模式下产生的热电荷载流子而在电介质区域中的电荷积累。 此外，提供场效应晶体管和包括场效应晶体管的电路配置。
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公开(公告)号：US09165921B2
公开(公告)日：2015-10-20
申请号：US13716784
申请日：2012-12-17
Applicant: Infineon Technologies AG
Inventor： Peter Nelle , Markus Zundel
CPC classification number: H01L29/7808 , H01L27/0629 , H01L29/0626 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/7813 , H01L29/8613
Abstract: One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of transistor cells in a semiconductor body. A width w3 of a transistor mesa region of each of the plurality of transistor cells and a width w1 of a first trench of each of the plurality of transistor cells satisfy the following relationship: w3
Abstract translation: 半导体器件的一个实施例包括致密沟槽晶体管单元阵列。 密集沟槽晶体管单元阵列包括半导体本体中的多个晶体管单元。 多个晶体管单元的晶体管台面区域的宽度w3和多个晶体管单元中的每一个的第一沟槽的宽度w1满足以下关系：w3 <1.5×w1。 半导体器件还包括半导体二极管。 至少一个半导体二极管布置在多个晶体管单元的第一和第二部分之间，并且包括邻接第二沟槽的相对壁的二极管台面区域。 第一沟槽的深度d1和第二沟槽的深度d2相差至少20％。
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公开(公告)号：US20140097431A1
公开(公告)日：2014-04-10
申请号：US14055982
申请日：2013-10-17
Applicant: Infineon Technologies AG
Inventor： Markus Zundel , Franz Hirler , Peter Nelle , Ludger Borucki , Markus Winkler , Erwin Vogl
IPC: H01L21/66
CPC classification number: H01L22/14 , H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential.
Abstract translation: 根据各种实施例的用于处理半导体器件的方法可以包括：提供具有第一焊盘和与第一焊盘电连接的第二焊盘的半导体器件; 对所述第一焊盘和所述第二焊盘中的至少一个施加至少一个电测试电位; 以及在施加所述至少一个电测试电位之后将所述第一焊盘和所述第二焊盘彼此电连接。
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公开(公告)号：US20140077262A1
公开(公告)日：2014-03-20
申请号：US14032437
申请日：2013-09-20
Applicant: Infineon Technologies AG
Inventor： Markus Zundel , Gabriela Brase , Peter Nelle , Guenther Schindler
IPC: H01L29/739
CPC classification number: H01L29/7393 , H01L23/3178 , H01L23/3192 , H01L29/0657 , H01L29/407 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.
Abstract translation: 本发明涉及半导体元件，其包括半导体本体，半导体主体上的绝缘体和至少部分地布置在半导体本体内的电池阵列。 电池阵列具有至少一个p-n结和至少一个接触连接。 绝缘体通过周向扩散阻挡层在半导体主体的横向方向上界定。
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公开(公告)号：US20150346270A1
公开(公告)日：2015-12-03
申请号：US14754738
申请日：2015-06-30
Applicant: Infineon Technologies AG
Inventor： Markus Zundel , Franz Hirler , Peter Nelle
IPC: G01R31/26
CPC classification number: G01R31/2601 , G01R31/2884 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.
Abstract translation: 根据一个或多个实施例的测试方法可以包括：提供待测试的半导体器件，所述半导体器件包括至少一个器件单元，所述至少一个器件单元具有至少一个沟槽，至少一个第一端子电极区域 以及至少一个第二端子电极区域，至少一个栅极电极和至少部分地设置在所述至少一个沟槽中的至少一个附加电极，其中所述至少一个附加电极的电势可以与电势分开地控制 所述至少一个第一端子电极区域，所述至少一个第二端子电极区域和所述至少一个栅极电极; 以及向至少一个附加电极施加至少一个电测试电位以检测所述至少一个器件单元中的缺陷。
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Patent Agency Ranking
公开(公告)号：US09099419B2
公开(公告)日：2015-08-04
申请号：US13647480
申请日：2012-10-09
Applicant: Infineon Technologies AG
Inventor： Markus Zundel , Franz Hirler , Peter Nelle
CPC classification number: G01R31/2601 , G01R31/2884 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.
Abstract translation: 根据一个或多个实施例的测试方法可以包括：提供待测试的半导体器件，所述半导体器件包括至少一个器件单元，所述至少一个器件单元具有至少一个沟槽，至少一个第一端子电极区域 以及至少一个第二端子电极区域，至少一个栅极电极和至少部分地设置在所述至少一个沟槽中的至少一个附加电极，其中所述至少一个附加电极的电势可以与电势分开地控制 所述至少一个第一端子电极区域，所述至少一个第二端子电极区域和所述至少一个栅极电极; 以及向至少一个附加电极施加至少一个电测试电位以检测所述至少一个器件单元中的缺陷。
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公开(公告)号：US09054150B2
公开(公告)日：2015-06-09
申请号：US14032437
申请日：2013-09-20
Applicant: Infineon Technologies AG
Inventor： Markus Zundel , Gabriela Brase , Peter Nelle , Guenther Schindler
IPC: H01L29/739 , H01L29/78 , H01L23/31 , H01L29/40 , H01L29/06
CPC classification number: H01L29/7393 , H01L23/3178 , H01L23/3192 , H01L29/0657 , H01L29/407 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.
Abstract translation: 本发明涉及半导体元件，其包括半导体本体，半导体主体上的绝缘体和至少部分地布置在半导体本体内的电池阵列。 电池阵列具有至少一个p-n结和至少一个接触连接。 绝缘体通过周向扩散阻挡层在半导体主体的横向方向上界定。
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公开(公告)号：US09429616B2
公开(公告)日：2016-08-30
申请号：US14754738
申请日：2015-06-30
Applicant: Infineon Technologies AG
Inventor： Markus Zundel , Franz Hirler , Peter Nelle
CPC classification number: G01R31/2601 , G01R31/2884 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.
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公开(公告)号：US20160013311A1
公开(公告)日：2016-01-14
申请号：US14862236
申请日：2015-09-23
Applicant: Infineon Technologies AG
Inventor： Peter Nelle , Markus Zundel
CPC classification number: H01L29/7808 , H01L27/0629 , H01L29/0626 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/7813 , H01L29/8613
Abstract: One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of transistor cells in a semiconductor body. A width w3 of a transistor mesa region of each of the plurality of transistor cells and a width w1 of a first trench of each of the plurality of transistor cells satisfy the following relationship: w3
Abstract translation: 半导体器件的一个实施例包括致密沟槽晶体管单元阵列。 密集沟槽晶体管单元阵列包括半导体本体中的多个晶体管单元。 多个晶体管单元的晶体管台面区域的宽度w3和多个晶体管单元中的每一个的第一沟槽的宽度w1满足以下关系：w3 <1.5×w1。 半导体器件还包括半导体二极管。 至少一个半导体二极管布置在多个晶体管单元的第一和第二部分之间，并且包括邻接第二沟槽的相对壁的二极管台面区域。 第一沟槽的深度d1和第二沟槽的深度d2相差至少20％。
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10.发明授权Method of manufacturing a semiconductor device including a stress relief layer 有权包括应力消除层的半导体器件的制造方法公开(公告)号：US09218960B2
公开(公告)日：2015-12-22
申请号：US14319534
申请日：2014-06-30
Applicant: Infineon Technologies AG
Inventor： Peter Nelle , Uwe Schmalzbauer , Juergen Holzmueller , Markus Zundel
CPC classification number: H01L21/02359 , H01L21/02129 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/78 , H01L23/29 , H01L23/3192 , H01L23/562 , H01L29/0603 , H01L2924/0002 , H01L2924/00
Abstract: A method of manufacturing a semiconductor device includes providing a layered structure having a hard dielectric layer containing a first dielectric material having a Young's modulus greater than 10 GPa in a central portion of a main surface of a main body comprising a single crystalline semiconductor body, and providing a dielectric stress relief layer containing a second dielectric material having a lower Young's modulus than the first dielectric material, the stress relief layer covering the layered structure and extending beyond an outer edge of the layered structure.
Abstract translation: 一种制造半导体器件的方法包括提供一种层状结构，其具有在包含单晶半导体主体的主体的主表面的中心部分中包含杨氏模量大于10GPa的第一介电材料的硬介电层，以及 提供包含具有比所述第一介电材料低的杨氏模量的第二介电材料的介电应力消除层，所述应力消除层覆盖所述层状结构并延伸超过所述层状结构的外边缘。
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