公开(公告)号：US09442558B2

公开(公告)日：2016-09-13

申请号：US14129950

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Paul S. Diefenbaugh ,  Eugene Gorbatov ,  Andrew Henroid ,  Eric C. Samson ,  Barnes Cooper

IPC: G06F1/32 ,  G06F9/48

CPC classification number: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

Abstract translation: 在一个实施例中，一种装置包括多个处理器组件; 通信地耦合到多个处理器组件的一个或多个处理器组件的一个或多个设备组件; 以及控制器，其包括其硬件中的至少一部分的逻辑，用于调度一个或多个强制空闲周期的逻辑，所述强制空闲周期与一个或多个活动周期分布，跨越持续时间的强制空闲周期，在该持续时间期间多个处理器组件和一个 或更多的设备组件同时处于分别在强制空闲时段的隔离子时段期间限定强制空闲功率状态的空闲状态。 公开和要求保护其他实施例。

公开(公告)号：US20150205344A1

公开(公告)日：2015-07-23

申请号：US14129950

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Paul S. Diefenbaugh ,  Eugene Gorbatov ,  Andrew Henroid ,  Eric C. Samson ,  Barnes Cooper

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

Abstract translation: 在一个实施例中，一种装置包括多个处理器组件; 通信地耦合到多个处理器组件的一个或多个处理器组件的一个或多个设备组件; 以及控制器，其包括其硬件中的至少一部分的逻辑，用于调度一个或多个强制空闲周期的逻辑，所述强制空闲周期与一个或多个活动周期分布，跨越持续时间的强制空闲周期，在该持续时间期间多个处理器组件和一个 或更多的设备组件同时处于分别在强制空闲时段的隔离子时段期间限定强制空闲功率状态的空闲状态。 公开和要求保护其他实施例。

公开(公告)号：US10761585B2

公开(公告)日：2020-09-01

申请号：US16158190

申请日：2018-10-11

Applicant: INTEL CORPORATION

Inventor： Paul S. Diefenbaugh ,  Eugene Gorbatov ,  Andrew Henroid ,  Eric C. Samson ,  Barnes Cooper

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3246 ,  G06F9/48

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

公开(公告)号：US10114441B2

公开(公告)日：2018-10-30

申请号：US15263274

申请日：2016-09-12

Applicant: INTEL CORPORATION

Inventor： Paul S. Diefenbaugh ,  Eugene Gorbatov ,  Andrew Henroid ,  Eric C. Samson ,  Barnes Cooper

IPC: G06F1/32 ,  G06F9/48

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.