公开(公告)号：US11953962B2

公开(公告)日：2024-04-09

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/50 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/324 ,  G06F9/5044 ,  G06F9/5094 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US20240028101A1

公开(公告)日：2024-01-25

申请号：US18477823

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3234 ,  G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/3234 ,  G06F1/324 ,  G06F1/3206

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US11853144B2

公开(公告)日：2023-12-26

申请号：US17664083

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/3234 ,  G06F1/324 ,  G06F1/3206

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US20230195918A1

公开(公告)日：2023-06-22

申请号：US17645070

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Stanley Chen ,  Vivek Garg ,  Ankush Varma ,  Eric J. Dehaemer ,  Johan van de Groenendaal

IPC: G06F21/62 ,  G06F9/30

CPC classification number: G06F21/6218 ,  G06F9/30101

Abstract: In an embodiment, a processor may include at least one processing engine to execute instructions, and a register interface circuit coupled to the at least one processing engine. The register interface circuit may be to: receive a request to access a register associated with a feature of the processor; determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor; and in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature. Other embodiments are described and claimed.

公开(公告)号：US11294852B2

公开(公告)日：2022-04-05

申请号：US16917888

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US11169560B2

公开(公告)日：2021-11-09

申请号：US16480830

申请日：2017-02-24

Applicant: INTEL CORPORATION

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris Macnamara ,  John J. Browne ,  Ripan Das

IPC: G06G1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324 ,  G06F1/08

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20200334193A1

公开(公告)日：2020-10-22

申请号：US16916197

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Guy G. Sotomayor ,  Andrew D. Henroid ,  Robert E. Gough ,  Tod F. Schiff

IPC: G06F15/00 ,  G06F1/20 ,  G06F1/3234 ,  G06F9/455 ,  G06F9/50

Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

公开(公告)号：US20190101969A1

公开(公告)日：2019-04-04

申请号：US15720801

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Krishnakanth V. Sistla ,  Ankush Varma ,  Ariel Szapiro

IPC: G06F1/30 ,  G06F1/32 ,  G06F12/084 ,  G06F12/0875

Abstract: In an embodiment, a processor includes a power control unit, a master processing engine, a set of slave processing engines, and a voltage regulator. The master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines. Other embodiments are described and claimed.

公开(公告)号：US09874922B2

公开(公告)日：2018-01-23

申请号：US14623764

申请日：2015-02-17

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Vasudevan Srinivasan ,  Eugene Gorbatov ,  Andrew D. Henroid ,  Barnes Cooper ,  David W. Browning ,  Guy M. Therien ,  Neil W. Songer ,  James G. Hermerding, II

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/50 ,  Y02B70/126 ,  Y02D10/171

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.

公开(公告)号：US09842082B2

公开(公告)日：2017-12-12

申请号：US14633455

申请日：2015-02-27

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Guy G. Sotomayor ,  Andrew D. Henroid ,  Robert E. Gough ,  Tod F. Schiff

IPC: G06F1/26 ,  G06F1/00 ,  G06F1/32 ,  G06F15/00 ,  G06F1/20 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F15/00 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3243 ,  G06F9/45541 ,  G06F9/45558 ,  G06F9/5077 ,  G06F2009/4557 ,  Y02D10/152 ,  Y02D10/16

Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.