公开(公告)号：US20230420384A1

公开(公告)日：2023-12-28

申请号：US17848639

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kavitha NAGARAJAN ,  Eng Huat GOH ,  Min Suet LIM ,  Telesphor KAMGAING ,  Chee Kheong YOON ,  Jooi Wah WONG ,  Chu Aun LIM

IPC: H01L23/552 ,  H01L23/367 ,  H01L23/16 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/367 ,  H01L23/16 ,  H01L23/562

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a stiffener for a surface of a semiconductor package, where the stiffener includes slots that allow a gasket to go over the stiffener to electrically couple with a ground or a VSS of the semiconductor package. In embodiments, the gasket may include a material that blocks or absorbs EMI or RFI. Other embodiments may be described and/or claimed.

公开(公告)号：US20220230958A1

公开(公告)日：2022-07-21

申请号：US17716937

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Poh Boon KHOO ,  Eng Huat GOH ,  Amruthavalli Pallavi ALUR ,  Debendra MALLIK

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20240106139A1

公开(公告)日：2024-03-28

申请号：US17955369

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Eng Huat GOH ,  Poh Boon KHOO ,  Chin Mian CHOONG ,  Jooi Wah WONG ,  Jia Yun WONG

IPC: H01R12/57 ,  H01L25/065 ,  H01L25/10 ,  H01R12/52 ,  H01R12/79 ,  H01R13/03 ,  H01R13/508 ,  H01R43/20

CPC classification number: H01R12/57 ,  H01L25/0652 ,  H01L25/105 ,  H01R12/526 ,  H01R12/79 ,  H01R13/03 ,  H01R13/508 ,  H01R43/205 ,  H01L24/16

Abstract: Embodiments herein relate to systems, apparatuses, or processes for a connector for a modular memory package that includes one or more memory dies on a substrate, where the connector directly electrically couples electrical contacts at an edge and on each side the substrate of the memory package to electrical contacts at an edge and on each side of another substrate that includes a compute die. The connector may include a first plurality of leads that are substantially parallel with each other, and a second plurality of leads that are substantially parallel with each other that are below the first plurality of leads and electrically couple the two substrates. Other embodiments may be described and/or claimed.

公开(公告)号：US20240071948A1

公开(公告)日：2024-02-29

申请号：US17895112

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Eng Huat GOH ,  Poh Boon KHOO ,  Nurul Khalidah YUSOP ,  Saw Beng TEOH ,  Chan Kim LEE

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/367 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package is provided including: a package substrate with a top surface, wherein the top surface extends to a peripheral side surface of the package substrate; a stiffener with a lateral portion and a basket portion, wherein the lateral portion is positioned over the top surface of the package substrate and the basket portion overhangs from the top surface of the package substrate adjacent to the peripheral side surface of the package substrate; at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener.

公开(公告)号：US20230395493A1

公开(公告)日：2023-12-07

申请号：US17833608

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Jooi Wah WONG ,  Eng Huat GOH ,  Telesphor KAMGAING ,  Chee Kheong YOON ,  Min Suet LIM ,  Kavitha NAGARAJAN ,  Chu Aun LIM

IPC: H01L23/528 ,  G11C11/4093

CPC classification number: H01L23/5283 ,  G11C11/4093

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, a package substrate comprises a core, a first layer on the core, where the first layer comprises a first plane, a second layer on the first layer, where the second layer comprises first traces and second traces arranged in an alternating pattern, a third layer on the second layer, where the third layer comprises third traces and fourth traces arranged in an alternating pattern, and a fourth layer over the third layer, where the fourth layer comprises a second plane.

公开(公告)号：US20240113033A1

公开(公告)日：2024-04-04

申请号：US17956753

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Jiun Hann SIR ,  Poh Boon KHOO ,  Hazwani JAFFAR ,  Hooi San LAM

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a die, which may be a processor die, coupled with a first side of a substrate and one or more dies, which may be one or more memory dies, that are coupled with a second side of the substrate opposite the first side of the substrate. All or part of the memory dies may be directly below the die with respect to a plane of the substrate and may be partially or completely within a molding. Other embodiments may be described and/or claimed.

公开(公告)号：US20230395578A1

公开(公告)日：2023-12-07

申请号：US17833600

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Min Suet LIM ,  Kavitha NAGARAJAN ,  Eng Huat GOH ,  Telesphor KAMGAING ,  Chee Kheong YOON ,  Jooi Wah WONG ,  Chu Aun LIM

IPC: H01L25/10 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2225/1035

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a base coupled to the package substrate. In an embodiment, a die is coupled to the base, and a memory die module is over the die. In an embodiment, the memory die module is communicatively coupled to the die through routing provided on the base

公开(公告)号：US20230395524A1

公开(公告)日：2023-12-07

申请号：US17833580

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Jiun Hann SIR ,  Chee Kheong YOON ,  Telesphor KAMGAING ,  Min Suet LIM ,  Kavitha NAGARAJAN ,  Chu Aun LIM

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L24/32 ,  H01L24/29 ,  H01L23/66 ,  H01L24/27 ,  H01L24/16 ,  H01L24/73 ,  H01L23/49822 ,  H01L2224/27515 ,  H01L2224/32227 ,  H01L2224/73204 ,  H01L2224/16235 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/3511 ,  H01L2924/3025 ,  H01L2924/2027 ,  H01L2924/1421 ,  H01L2224/32237 ,  H01L2224/29018 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2924/0781

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, a stiffener is around the die and over the package substrate. In an embodiment, an electrically non-conductive underfill is around first level interconnects (FLIs) between the package substrate and the die. In an embodiment, an electrically conductive layer is around the non-conductive underfill.

公开(公告)号：US20220078911A1

公开(公告)日：2022-03-10

申请号：US17090911

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Tin Poay CHUAH ,  Min Suet LIM ,  Chee Chun YEE ,  Yew San LIM ,  Eng Huat GOH

IPC: H05K1/11 ,  H05K1/14

Abstract: A multilayer printed circuit board including a first printed circuit board portion, including a first inserting connector, including a plurality of contacts for creating a first removable bus connection; a second printed circuit board portion, including a second inserting connector, including a plurality of contacts for creating a second removable bus connection; a third printed circuit board portion, connected between the first printed circuit board portion and to the second printed circuit board portion, wherein a rigidity of the third printed circuit board portion is less than a rigidity of each of the first printed circuit board portion and the second printed circuit board portion; wherein the multilayer printed circuit board is foldable along the third printed circuit board portion and, if so folded, the first printed circuit board portion is arranged on top of the second printed circuit board portion.

公开(公告)号：US20210202380A1

公开(公告)日：2021-07-01

申请号：US17200700

申请日：2021-03-12

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Poh Boon KHOO ,  Eng Huat GOH ,  Amruthavalli Pallavi ALUR ,  Debendra MALLIK

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.