公开(公告)号：US11557536B2

公开(公告)日：2023-01-17

申请号：US16649901

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Christopher J. Jezewski ,  Manish Chandhok

IPC: H01L23/522 ,  H01L21/768

Abstract: Integrated circuit (IC) interconnect lines having improved electromigration resistance. Multi-patterning may be employed to define a first mask pattern. The first mask pattern may be backfilled and further patterned based on a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of material underlying openings defined in the second mask layer that exceed the threshold are removed. First trenches in an underlying dielectric material layer may be etched based on a union of the remainder of the first mask layer and the partially occluded second mask layer. The first trenches may then be backfilled with a first conductive material to form first line segments. Additional trenches in the underlayer may then be etched and backfilled with a second conductive material to form second line segments that are coupled together by the first line segments.

公开(公告)号：US11482622B2

公开(公告)日：2022-10-25

申请号：US16214706

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Kevin Lin ,  Abhishek Sharma ,  Carl Naylor ,  Urusa Alaan ,  Christopher Jezewski ,  Ashish Agrawal

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/24 ,  H01L29/417

Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.

公开(公告)号：US11367682B2

公开(公告)日：2022-06-21

申请号：US16329738

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: This disclosure is directed to systems and methods for maskless gap integration in interconnects having one or more vias above one or more interconnect lines (for example, metal interconnect lines). In various embodiments, the systems and methods described in the disclosure may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines from electrical shorting during subsequent metal layer depositions in a fabrication sequence of the interconnects. Further, in various embodiments, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps, for example, without the need for additional lithography steps.

公开(公告)号：US20220139823A1

公开(公告)日：2022-05-05

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11152514B2

公开(公告)日：2021-10-19

申请号：US16640340

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Gilbert Dewey ,  Kent Millard ,  Jack Kavalieros ,  Shriram Shivaraman ,  Tristan A. Tronic ,  Sanaz Gardner ,  Justin R. Weber ,  Tahir Ghani ,  Li Huey Tan ,  Kevin Lin

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267

Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

公开(公告)号：US11152254B2

公开(公告)日：2021-10-19

申请号：US16463816

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Manish Chandhok ,  Sudipto Naskar ,  Stephanie A. Bojarski ,  Kevin Lin ,  Marie Krysak ,  Tristan A. Tronic ,  Hui Jae Yoo ,  Jeffery D. Bielefeld ,  Jessica M. Torres

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.

公开(公告)号：US10593627B2

公开(公告)日：2020-03-17

申请号：US15574816

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Kanwal Jit Singh ,  Kevin Lin ,  Robert Lindsey Bristol

IPC: H01L23/532 ,  H01L29/06 ,  H01L23/522 ,  H01L21/768 ,  H01L23/498 ,  H01L21/764

Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.

公开(公告)号：US10553532B2

公开(公告)日：2020-02-04

申请号：US15529484

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Richard E. Schenker ,  Manish Chandhok ,  Robert L. Bristol ,  Mauro J. Kobrinsky ,  Kevin Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/532

Abstract: Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.

公开(公告)号：US09513529B2

公开(公告)日：2016-12-06

申请号：US14128926

申请日：2013-08-20

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Nathan R. Andrysco

IPC: G02F1/03 ,  G02F1/07 ,  G02F1/19

CPC classification number: G02F1/19 ,  G02B26/0841

Abstract: Embodiments of the present disclosure provide techniques and configurations for a display apparatus. In one embodiment, the apparatus may include one or more micro-electro-mechanical system (MEMS) devices. The MEMS device may include a first electrode including a partially reflective surface, a second electrode including a partially or completely reflective surface and disposed substantially parallel to the first electrode, and an analog actuation arrangement coupled to the first electrode, the second electrode or both the first and second electrodes to cause movement of the first electrode from a start position to a selected position of a plurality of end positions, responsive to a selected application of an actuation voltage, to cause the MEMS device to selectively output a reflection of a light in a selected wavelength, or no reflection of the light. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了用于显示装置的技术和配置。 在一个实施例中，该装置可以包括一个或多个微机电系统（MEMS）装置。 MEMS器件可以包括包括部分反射表面的第一电极，包括部分或完全反射表面并且基本上平行于第一电极设置的第二电极，以及耦合到第一电极，第二电极或两者的模拟致动装置 第一和第二电极，以响应于所选择的致动电压的应用，使第一电极从起始位置移动到多个端部位置的选定位置，以使MEMS器件选择性地输出光的反射 选择的波长，或没有光的反射。 可以描述和/或要求保护其他实施例。

公开(公告)号：US12027458B2

公开(公告)日：2024-07-02

申请号：US17841551

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53209

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.