公开(公告)号：US20200051724A1

公开(公告)日：2020-02-13

申请号：US15735622

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC: H01F10/193 ,  H01F10/32 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.

公开(公告)号：US10559744B2

公开(公告)日：2020-02-11

申请号：US16072301

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Brian Maertz ,  Christopher J. Wiegand ,  Daniel G. Oeullette ,  Md Tofizur Rahman ,  Oleg Golonzka ,  Justin S. Brockman ,  Tahir Ghani ,  Brian S. Doyle ,  Kevin P. O'Brien ,  Mark L. Doczy ,  Kaan Oguz

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

公开(公告)号：US10381556B2

公开(公告)日：2019-08-13

申请号：US15753478

申请日：2015-09-18

Applicant: INTEL CORPORATION

Inventor： Mark L. Doczy ,  Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Kevin P. O'Brien ,  Satyarth Suri ,  Tejaswi K. Indukuri

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/10

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US10367093B2

公开(公告)日：2019-07-30

申请号：US15730542

申请日：2017-10-11

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H04B1/3827

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US20180047846A1

公开(公告)日：2018-02-15

申请号：US15730542

申请日：2017-10-11

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H04B1/3827 ,  H01L29/06 ,  H01L29/10 ,  H01L29/267

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US09779794B2

公开(公告)日：2017-10-03

申请号：US15116457

申请日：2014-03-26

Applicant: INTEL CORPORATION

Inventor： Brian S. Doyle ,  David L. Kencke ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Charles C. Kuo ,  Roksana Golizadeh Mojarad

IPC: H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

CPC classification number: G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.

公开(公告)号：US20170170318A1

公开(公告)日：2017-06-15

申请号：US15442087

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L29/51 ,  H01L29/08 ,  H01L29/267 ,  H01L29/207

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US20160197185A1

公开(公告)日：2016-07-07

申请号：US15069726

申请日：2016-03-14

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H04B1/3827 ,  H01L29/267 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract translation: 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。

公开(公告)号：US20210135007A1

公开(公告)日：2021-05-06

申请号：US17148330

申请日：2021-01-13

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H04B1/3827

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US10937907B2

公开(公告)日：2021-03-02

申请号：US16526898

申请日：2019-07-30

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H04B1/3827

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.