公开(公告)号：US11169560B2

公开(公告)日：2021-11-09

申请号：US16480830

申请日：2017-02-24

Applicant: INTEL CORPORATION

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris Macnamara ,  John J. Browne ,  Ripan Das

IPC: G06G1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324 ,  G06F1/08

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US12298833B2

公开(公告)日：2025-05-13

申请号：US18007627

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Ujjwal Gupta ,  Ankush Varma ,  Lakshmipriya Seshan ,  Nikethan Shivanand Baligar ,  Nikhil Gupta ,  Swadesh Choudhary ,  Yogesh Bansal

IPC: G06F1/324 ,  G06F1/10 ,  G06F1/3203 ,  G06F11/34 ,  G06F13/00 ,  G06F15/16

Abstract: A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

公开(公告)号：US11726910B2

公开(公告)日：2023-08-15

申请号：US16816779

申请日：2020-03-12

Applicant: Intel Corporation

Inventor： Ian M. Steiner ,  Andrew J. Herdrich ,  Wenhui Shu ,  Ripan Das ,  Dianjun Sun ,  Nikhil Gupta ,  Shruthi Venugopal

IPC: G06F12/06 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F12/0646 ,  G06F11/3037 ,  G06F11/3495 ,  G06F2212/1044

Abstract: Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

公开(公告)号：US11567556B2

公开(公告)日：2023-01-31

申请号：US16833008

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Chris Macnamara ,  John J. Browne ,  Tomasz Kantecki ,  David Hunt ,  Anatoly Burakov ,  Srihari Makineni ,  Nikhil Gupta ,  Ankush Varma ,  Dorit Shapira ,  Vasudevan Srinivasan ,  Bryan T. Butters ,  Shrikant M. Shah

IPC: G06F1/324 ,  G06F1/20 ,  G06F9/50 ,  G06F1/3296

Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

公开(公告)号：US11301298B2

公开(公告)日：2022-04-12

申请号：US16833595

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Krishnakanth Sistla ,  Nilanjan Palit ,  Abhinav Karhu ,  Eugene Gorbatov ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

公开(公告)号：US10976801B2

公开(公告)日：2021-04-13

申请号：US16136440

申请日：2018-09-20

Applicant: Intel Corporation

Inventor： Avinash Ananthakrishnan ,  Nikhil Gupta

IPC: G06F1/00 ,  G06F1/3287 ,  G06F9/48 ,  G06F1/3293 ,  G06F1/3234 ,  G06F1/3203 ,  G06F9/50 ,  G06F1/324

Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions, at least some of the plurality of cores to be allocated to a plurality of virtual machines (VMs); and a power controller coupled to the plurality of cores. The power controller may include a power distribution circuit to distribute an energy budget to the at least some of the plurality of cores according to priority information associated with the plurality of VMs. Other embodiments are described and claimed.

公开(公告)号：US20200319693A1

公开(公告)日：2020-10-08

申请号：US16853570

申请日：2020-04-20

Applicant: Intel Corporation

Inventor： Asma Al-Rawi ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Nikhil Gupta ,  Ankush Varma ,  Krishnakanth V. Sistla ,  Ian M. Steiner

IPC: G06F1/3206 ,  G06F1/324 ,  H04L12/12 ,  G06F1/3228 ,  G06F1/20

Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.

公开(公告)号：US20190041949A1

公开(公告)日：2019-02-07

申请号：US15866425

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Asma Al-Rawi ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Nikhil Gupta ,  Ankush Varma ,  Krishnakanth V. Sistla ,  Ian M. Steiner

IPC: G06F1/32 ,  H04L12/12

Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.

公开(公告)号：US20180373287A1

公开(公告)日：2018-12-27

申请号：US15632000

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Asma H. Al-Rawi ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Dorit Shapira ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Chris MacNamara

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F9/50

Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.

公开(公告)号：US20180365022A1

公开(公告)日：2018-12-20

申请号：US15625423

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Nikhil Gupta ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Vasudevan Srinivasan ,  Eliezer Weissmann ,  Stephen H. Gunther ,  Eugene Gorbatov ,  Russell J. Fenger ,  Guy M. Therien

IPC: G06F9/44 ,  G06F3/06

Abstract: Embodiments of processors, methods, and systems for dynamic offlining and onlining of processor cores are described. In an embodiment, a processor includes a plurality of cores, a core status storage location, and a core tracker. Core status information for at least one of the plurality of cores is the be stored in the core status storage location. The core status information is to include a core state to be used by a software scheduler. The core state is to be one of a plurality of core state values including an online value, a requesting-to-go-offline value, and an offline value. The core tracker is to track usage of the at least one core and to change the core state from the online value to the requesting-to-go-offline value in response to determining that usage has reached a predetermined threshold.