公开(公告)号：US11106262B2

公开(公告)日：2021-08-31

申请号：US16421647

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/20 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50 ,  G06F1/3203 ,  G06F1/3234

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

公开(公告)号：US20190354160A1

公开(公告)日：2019-11-21

申请号：US16421647

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/3206 ,  G06F1/20 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50 ,  G06F1/3203

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

公开(公告)号：US08904205B2

公开(公告)日：2014-12-02

申请号：US14171148

申请日：2014-02-03

Applicant: Intel Corporation

Inventor： James S. Burns ,  Baskaran Ganesan ,  Russell J. Fenger ,  Devadatta V. Bodas ,  Sundaravarathan R. Iyengar ,  Feranak Nelson ,  John M. Powell, Jr. ,  Suresh Sugumar

IPC: G06F1/00 ,  G06F9/46 ,  G06F1/26 ,  G06F9/50 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24

Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

公开(公告)号：US20210373638A1

公开(公告)日：2021-12-02

申请号：US17402927

申请日：2021-08-16

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/3206 ,  G06F1/20 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50 ,  G06F1/3203 ,  G06F1/3234

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

公开(公告)号：US10372493B2

公开(公告)日：2019-08-06

申请号：US14978182

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Vijay Dhanraj ,  Gaurav Khanna ,  Russell J. Fenger ,  Monica Gupta

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/50

Abstract: Apparatuses, methods and storage medium associated with scheduling of threads and/or virtual machines, are disclosed herein. In embodiments, an apparatus is provided with a scheduler of an operating system and/or a virtual machine monitor. The scheduler is to retrieve or receive capabilities of the cores of one or more multi-core processors of the apparatus with diverse capabilities, and schedule a plurality of threads for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and characteristics of the plurality of threads. The virtual machine monitor is to retrieve or receive capabilities of the cores, and schedule a plurality of virtual machines for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and respective priorities of the virtual machines. Other embodiments may be described and/or claimed.

公开(公告)号：US20190102221A1

公开(公告)日：2019-04-04

申请号：US15720296

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunter ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US09639372B2

公开(公告)日：2017-05-02

申请号：US13730565

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3891

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

公开(公告)号：US10317976B2

公开(公告)日：2019-06-11

申请号：US15611876

申请日：2017-06-02

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/32 ,  G06F9/50 ,  G06F1/3206 ,  G06F1/20 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3203 ,  G06F1/3234

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

公开(公告)号：US20190102229A1

公开(公告)日：2019-04-04

申请号：US15721858

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Russell J. Fenger ,  Vijay Dhanraj ,  Deepak Samuel Kirubakaran ,  Srividya Ambale ,  Israel Hirsh ,  Eliezer Weissmann ,  Hisham Abu-Salah

IPC: G06F9/50

Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

公开(公告)号：US20170364133A1

公开(公告)日：2017-12-21

申请号：US15611876

申请日：2017-06-02

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/32 ,  G06F1/20 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.