公开(公告)号：US20220406773A1

公开(公告)日：2022-12-22

申请号：US17353275

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Kalyan C. KOLLURU ,  Mauro J. KOBRINSKY ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L23/48 ,  H01L21/8234

Abstract: Integrated circuit structures having backside self-aligned conductive pass-through contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive pass-through contacts, are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A dummy gate electrode is laterally between the first stack of nanowires and the second stack of nanowires. A conductive pass-through contact is laterally between the first stack of nanowires and the second stack of nanowires. The conductive pass-through contact is on and in contact with the dummy gate electrode.

公开(公告)号：US20210167066A1

公开(公告)日：2021-06-03

申请号：US16700064

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Harshitha VISHWANATH ,  Renukprasad HIREMATH ,  Sukru YEMENICIOGLU ,  Ranjith KUMAR ,  Ruth Amy BRAIN

IPC: H01L27/092 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate, and a cell on the substrate. In an embodiment, the cell comprises a plurality of transistors over the substrate, and a first metal layer over the plurality of transistors. In an embodiment, the first metal layer comprises a first power line, wherein a width of the first power line is entirely within the cell, a second power line, wherein a width of the second power line is entirely within the cell, and a plurality of signal lines between the first power line and the second power line.

公开(公告)号：US20240113233A1

公开(公告)日：2024-04-04

申请号：US17958290

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Shengsi LIU ,  Shao Ming KOH ,  Tahir GHANI

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/785

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for techniques for creating a wall within a forkFET transistor structure, where the wall is adjacent to a first stack of nanoribbons on a first side of the wall and a second stack of nanoribbons on a second side of the wall opposite the first side of the wall. In embodiments, the wall extends beyond the top of the first stack of nanoribbons and electrically isolates a first gate metal coupled with the first stack of nanoribbons and a second gate metal coupled with the second stack of nanoribbons from each other. Other embodiments may be described and/or claimed.

公开(公告)号：US20240113108A1

公开(公告)日：2024-04-04

申请号：US17958285

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Leonard P. GULER ,  Hongqian SUN ,  Shengsi LIU ,  Tahir GHANI ,  Baofu ZHU

IPC: H01L27/088 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/764 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a wall within a metal gate cut in a transistor layer of a semiconductor device, where the wall includes a volume of a gas such as air, nitrogen, or another inert gas. Other embodiments may be described and/or claimed.

公开(公告)号：US20230317595A1

公开(公告)日：2023-10-05

申请号：US17710817

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Makram ABD EL QADER ,  Tahir GHANI ,  Chanaka D. MUNASINGHE

IPC: H01L23/522 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L29/0673 ,  H01L27/0886 ,  H01L23/5283

Abstract: Integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends to the conductive trench contact structure. The conductive via has an uppermost surface above an uppermost surface of the epitaxial source or drain structure.

公开(公告)号：US20240355819A1

公开(公告)日：2024-10-24

申请号：US18760970

申请日：2024-07-01

Applicant: Intel Corporation

Inventor： Quan SHI ,  Sukru YEMENICIOGLU ,  Marni NABORS ,  Nikolay RYZHENKO ,  Xinning WANG ,  Sivakumar VENKATARAMAN

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/50 ,  H01L29/0669 ,  H01L29/785 ,  H01L2029/7858

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

公开(公告)号：US20240113111A1

公开(公告)日：2024-04-04

申请号：US17956779

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Clifford ONG ,  Sukru YEMENICIOGLU ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/78696

Abstract: Integrated circuit structures having fin isolation regions recessed for gate contact are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A dielectric gate cut plug is between the gate structure and the dielectric structure. A recess is in the dielectric structure and in the dielectric gate cut plug. A conductive structure is in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.

公开(公告)号：US20240105716A1

公开(公告)日：2024-03-28

申请号：US17954206

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Mohit K. HARAN ,  Stephen M. CEA ,  Charles H. WALLACE ,  Tahir GHANI ,  Shengsi LIU ,  Saurabh ACHARYA ,  Thomas O'BRIEN ,  Nidhi KHANDELWAL ,  Marie T. CONTE ,  Prabhjot LUTHRA

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L21/823481

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

公开(公告)号：US20230317787A1

公开(公告)日：2023-10-05

申请号：US17709374

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mauro J. KOBRINSKY ,  Mohit K. HARAN ,  Marni NABORS ,  Tahir GHANI ,  Charles H. WALLACE ,  Allen B. GARDINER ,  Sukru YEMENICIOGLU

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L27/0886

Abstract: Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.

公开(公告)号：US20240105801A1

公开(公告)日：2024-03-28

申请号：US17951974

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Raghuram GANDIKOTA ,  Krishna GANESAN ,  Sean PURSEL

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/775 ,  H01L2029/42388

Abstract: Integrated circuit structures having gate volume reduction, and methods of fabricating integrated circuit structures having gate volume reduction, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first side and a second side. A dielectric backbone structure is along the first side of the stack of nanowires. The dielectric backbone structure has a bottom above a bottom of the sub-fin. A gate electrode is over the stack of nanowires and is along the second side of the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires.