公开(公告)号：US10831674B2

公开(公告)日：2020-11-10

申请号：US15844164

申请日：2017-12-15

Applicant: International Business Machines Corporation

Inventor： Markus Helms ,  Christian Jacobi ,  Ulrich Mayer ,  Martin Recktenwald ,  Johannes C. Reichart ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/1045 ,  G06F12/0864 ,  G06F12/0842 ,  G06F12/0808 ,  G06F12/0817 ,  G06F12/1009 ,  G06F12/0897 ,  G06F12/0811

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

公开(公告)号：US10810134B2

公开(公告)日：2020-10-20

申请号：US15844239

申请日：2017-12-15

Applicant: International Business Machines Corporation

Inventor： Markus Helms ,  Christian Jacobi ,  Martin Recktenwald ,  Johannes C. Reichart

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/08 ,  G06F12/1027 ,  G06F12/0875 ,  G06F12/1009

Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

公开(公告)号：US10606762B2

公开(公告)日：2020-03-31

申请号：US15625336

申请日：2017-06-16

Applicant: International Business Machines Corporation

Inventor： Markus Helms ,  Christian Jacobi ,  Martin Recktenwald ,  Johannes C. Reichart

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/08 ,  G06F12/1027 ,  G06F12/0875 ,  G06F12/1009

Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

公开(公告)号：US20190243894A1

公开(公告)日：2019-08-08

申请号：US16384449

申请日：2019-04-15

Applicant: International Business Machines Corporation

Inventor： Jonathan D. Bradbury ,  Markus Helms ,  Christian Jacobi ,  Aditya N. Puranik ,  Christian Zoellin

IPC: G06F17/27 ,  G06F16/901 ,  G06F16/23 ,  H03M7/30 ,  G06F3/06 ,  H03M7/40

CPC classification number: G06F17/2705 ,  G06F3/0608 ,  G06F3/0626 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F16/2365 ,  G06F16/9027 ,  H03M7/3079 ,  H03M7/3088 ,  H03M7/40

Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

公开(公告)号：US20180365171A1

公开(公告)日：2018-12-20

申请号：US15811807

申请日：2017-11-14

Applicant: International Business Machines Corporation

Inventor： Uwe Brandt ,  Markus Helms ,  Thomas Köhler ,  Frank Lehnert

IPC: G06F12/1045 ,  G06F12/0891

CPC classification number: G06F12/1063 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/123 ,  G06F2212/1021 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/683

Abstract: A computer-implemented method includes associating an initial use order with a plurality of target sets of a translation lookaside buffer (TLB), where the initial use order indicates an order of use of the plurality of target sets. The plurality of target sets are associated with an initial least-recently-used (LRU) state based on the initial use order. A new use order for the plurality of target sets is generated. Generating the new use order includes moving a first target set to a least-recently-used position, responsive to a purge of the first target set. The LRU state of the plurality of target sets is updated based on the new use order, responsive to the purge of the first target set. The first target set is identified as eligible for replacement according to an LRU replacement policy of the TLB, based at least in part on the purge of the first target set.

公开(公告)号：US20180365170A1

公开(公告)日：2018-12-20

申请号：US15625289

申请日：2017-06-16

Applicant: International Business Machines Corporation

Inventor： Markus Helms ,  Christian Jacobi ,  Ulrich Mayer ,  Martin Recktenwald ,  Johannes C. Reichart ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/1045 ,  G06F12/0808 ,  G06F12/0817 ,  G06F12/1009 ,  G06F12/0811

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

公开(公告)号：US20180365165A1

公开(公告)日：2018-12-20

申请号：US15856140

申请日：2017-12-28

Applicant: International Business Machines Corporation

Inventor： Uwe Brandt ,  Ute Gaertner ,  Lisa C. Heller ,  Markus Helms ,  Thomas Köhler ,  Frank Lehnert ,  Jennifer A. Navarro ,  Rebecca S. Wisniewski

IPC: G06F12/1027 ,  G06F12/1009

Abstract: Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

公开(公告)号：US09898348B2

公开(公告)日：2018-02-20

申请号：US14520505

申请日：2014-10-22

Applicant: International Business Machines Corporation

Inventor： Khary J. Alexander ,  Markus Helms ,  Christian Jacobi ,  Bernd Nerz ,  Volker Urban

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F12/00 ,  G06F9/52 ,  G06F9/44 ,  G06F9/45

CPC classification number: G06F9/52 ,  G06F8/10 ,  G06F8/314 ,  G06F8/45 ,  G06F9/5077

Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.

公开(公告)号：US11263398B2

公开(公告)日：2022-03-01

申请号：US16384449

申请日：2019-04-15

Applicant: International Business Machines Corporation

Inventor： Jonathan D. Bradbury ,  Markus Helms ,  Christian Jacobi ,  Aditya N. Puranik ,  Christian Zoellin

IPC: G06F3/00 ,  G06F40/205 ,  G06F16/23 ,  G06F16/901 ,  H03M7/30 ,  G06F3/06 ,  H03M7/40

Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

公开(公告)号：US20210026783A1

公开(公告)日：2021-01-28

申请号：US17069290

申请日：2020-10-13

Applicant: International Business Machines Corporation

Inventor： Markus Helms ,  Christian Jacobi ,  Ulrich Mayer ,  Martin Recktenwald ,  Johannes C. Reichart ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/1045 ,  G06F12/0864 ,  G06F12/0842 ,  G06F12/0808 ,  G06F12/0817 ,  G06F12/1009

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.