公开(公告)号：US20240378171A1

公开(公告)日：2024-11-14

申请号：US18781120

申请日：2024-07-23

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F15/177 ,  G05B19/04 ,  G05B19/045 ,  G06F1/32 ,  G06F9/44 ,  G06F9/4401 ,  G06F13/12 ,  G06F15/17 ,  G06F15/78

Abstract: An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

公开(公告)号：US11416442B2

公开(公告)日：2022-08-16

申请号：US17135502

申请日：2020-12-28

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F9/44 ,  G06F13/12 ,  G06F15/17 ,  G06F15/177 ,  G06F15/78 ,  G05B19/045 ,  G05B19/04 ,  G06F9/4401 ,  G06F1/32

Abstract: An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

公开(公告)号：US20220327093A1

公开(公告)日：2022-10-13

申请号：US17852264

申请日：2022-06-28

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F15/177 ,  G06F15/17 ,  G06F13/12 ,  G06F9/44 ,  G05B19/045 ,  G06F15/78 ,  G05B19/04 ,  G06F9/4401

Abstract: An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

公开(公告)号：US20210117367A1

公开(公告)日：2021-04-22

申请号：US17135502

申请日：2020-12-28

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F15/177 ,  G06F15/17 ,  G06F13/12 ,  G06F9/44 ,  G05B19/045 ,  G06F15/78 ,  G05B19/04 ,  G06F9/4401

Abstract: An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

公开(公告)号：US20200183866A1

公开(公告)日：2020-06-11

申请号：US16788933

申请日：2020-02-12

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F13/24 ,  G06F13/40 ,  G06F15/78

Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

公开(公告)号：US11429546B2

公开(公告)日：2022-08-30

申请号：US17222783

申请日：2021-04-05

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F13/24 ,  G06F15/78 ,  G06F13/40

Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

公开(公告)号：US12072833B2

公开(公告)日：2024-08-27

申请号：US17852264

申请日：2022-06-28

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F9/44 ,  G05B19/04 ,  G05B19/045 ,  G06F9/4401 ,  G06F13/12 ,  G06F15/17 ,  G06F15/177 ,  G06F15/78 ,  G06F1/32

CPC classification number: G06F15/177 ,  G05B19/04 ,  G05B19/045 ,  G06F9/44 ,  G06F9/4411 ,  G06F13/12 ,  G06F13/124 ,  G06F15/17 ,  G06F15/78 ,  G06F15/7821 ,  G06F1/32 ,  Y02D10/00

Abstract: An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

公开(公告)号：US20210224208A1

公开(公告)日：2021-07-22

申请号：US17222783

申请日：2021-04-05

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F13/24 ,  G06F15/78 ,  G06F13/40

Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

公开(公告)号：US20170308502A1

公开(公告)日：2017-10-26

申请号：US15496217

申请日：2017-04-25

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F15/177 ,  G06F9/44 ,  G06F13/12 ,  G06F15/78

CPC classification number: G06F15/177 ,  G06F9/4411 ,  G06F13/124 ,  G06F15/7821 ,  Y02D10/14

Abstract: An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

公开(公告)号：US11868290B2

公开(公告)日：2024-01-09

申请号：US17886396

申请日：2022-08-11

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F13/24 ,  G06F15/78 ,  G06F13/40

CPC classification number: G06F13/24 ,  G06F13/404 ,  G06F15/7807 ,  Y02D10/00

Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.