公开(公告)号：US10387155B2

公开(公告)日：2019-08-20

申请号：US15079269

申请日：2016-03-24

Applicant: Imagination Technologies Limited

Inventor： Paul Murrin ,  Gareth Davies ,  Adrian J. Anderson

IPC: G06F9/30 ,  G06F15/76 ,  G06F15/167

Abstract: A processing system includes a program processor for executing a program, and a dedicated processor for executing operations of a particular type (e.g. vector processing operations). The program processor uses an interfacing module and a group of two or more register banks to offload operations of the particular type to the dedicated processor for execution thereon. While the dedicated processor is accessing one register bank for executing a current operation, the interfacing module can concurrently load data for a subsequent operation into a different one of the register banks. The use of multiple register banks allows the dedicated processor to spend a greater proportion of its time executing operations.

公开(公告)号：US10255161B2

公开(公告)日：2019-04-09

申请号：US15079580

申请日：2016-03-24

Applicant: Imagination Technologies Limited

Inventor： Paul Murrin ,  Gareth Davies

IPC: G06F11/00 ,  G06F11/36 ,  G06F17/40 ,  G06F11/34

Abstract: A logging unit is used to log entries for events in a computer system. Each entry includes an n-bit timestamp field and a payload. The payload includes information about the event and the timestamp field includes the n least significant bits of an N-bit timestamp for the event, where N>n. If the n least significant bits of the timestamp have wrapped compared to the corresponding n bits of the timestamp of the preceding entry then a timing entry is logged which includes other bits of the timestamp. Therefore, an N-bit timestamp can be determined for an event, but only the n least significant bits of the timestamp are stored in the timestamp field of an entry for the event. Therefore, the time flow of events in the store is better maintained (by having a larger timestamp) without increasing the number of bits (n) in the timestamp field of each entry.

公开(公告)号：US20160283312A1

公开(公告)日：2016-09-29

申请号：US15079580

申请日：2016-03-24

Applicant: Imagination Technologies Limited

Inventor： Paul Murrin ,  Gareth Davies

IPC: G06F11/07

CPC classification number: G06F11/3636 ,  G06F11/3466 ,  G06F11/3476 ,  G06F17/40 ,  G06F2201/835 ,  G06F2201/86

Abstract: A logging unit is used to log entries for events in a computer system. Each entry includes an n-bit timestamp field and a payload. The payload includes information about the event and the timestamp field includes the n least significant bits of an N-bit timestamp for the event, where N>n. If the n least significant bits of the timestamp have wrapped compared to the corresponding n bits of the timestamp of the preceding entry then a timing entry is logged which includes other bits of the timestamp. Therefore, an N-bit timestamp can be determined for an event, but only the n least significant bits of the timestamp are stored in the timestamp field of an entry for the event. Therefore, the time flow of events in the store is better maintained (by having a larger timestamp) without increasing the number of bits (n) in the timestamp field of each entry.

Abstract translation: 记录单元用于记录计算机系统中事件的条目。 每个条目包括n位时间戳字段和有效载荷。 有效载荷包括关于事件的信息，并且时间戳字段包括事件的N位时间戳的n个最低有效位，其中N> n。 如果时间戳的n个最低有效位与先前条目的时间戳的相应n位相比较，则记录包括时间戳的其他位的定时条目。 因此，可以为事件确定N位时间戳，但是时间戳的n个最低有效位仅存储在事件的条目的时间戳字段中。 因此，在不增加每个条目的时间戳字段中的位数（n）的情况下，更好地维持存储器中的事件的时间流（通过具有较大的时间戳）。

公开(公告)号：US20160283235A1

公开(公告)日：2016-09-29

申请号：US15079269

申请日：2016-03-24

Applicant: Imagination Technologies Limited

Inventor： Paul Murrin ,  Gareth Davies ,  Adrian J. Anderson

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/30098 ,  G06F15/167 ,  G06F15/76

Abstract: A processing system includes a program processor for executing a program, and a dedicated processor for executing operations of a particular type (e.g. vector processing operations). The program processor uses an interfacing module and a group of two or more register banks to offload operations of the particular type to the dedicated processor for execution thereon. Whilst the dedicated processor is accessing one register bank for executing a current operation, the interfacing module can concurrently load data for a subsequent operation into a different one of the register banks. The use of multiple register banks allows the dedicated processor to spend a greater proportion of its time executing operations.

Abstract translation: 处理系统包括用于执行程序的程序处理器和用于执行特定类型（例如向量处理操作）的操作的专用处理器。 程序处理器使用接口模块和一组两个或多个寄存器组来将特定类型的操作卸载到专用处理器以便在其上执行。 当专用处理器访问一个寄存器组以执行当前操作时，接口模块可以同时将用于后续操作的数据加载到不同的寄存器组中。 使用多个寄存器组允许专用处理器花费更多的时间执行操作。

公开(公告)号：US20160283439A1

公开(公告)日：2016-09-29

申请号：US15081007

申请日：2016-03-25

Applicant: Imagination Technologies Limited

Inventor： Paul Murrin ,  Gareth Davies ,  Adrian J. Anderson

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/8007 ,  G06F9/30036 ,  G06F9/3012 ,  G06F9/381 ,  G06F9/3887

Abstract: A SIMD processing module is provided, comprising multiple vector processing units (“VUs”), which can be used to execute an instruction on respective parts (or “subvectors”) within a vector. A control unit determines a vector position indication for each of the VUs to indicate which part of the vector that VU is to execute the instruction on. Therefore, the vector is conceptually divided into subvectors with the respective VUs executing the instruction on the respective subvectors in parallel. Each VU can then execute the instruction as intended, but only on a subsection of the whole vector. This allows an instruction that is written for execution on an n-way VU to be executed by multiple n-way VUs, each starting at different points of the vector, such that the instruction can be executed on more than n of the data items of the vector in parallel.

Abstract translation: 提供了一种SIMD处理模块，其包括多个向量处理单元（“VU”），其可用于对向量内的相应部分（或“子向量”）执行指令。 控制单元确定每个VU的向量位置指示，以指示VU要执行指令的向量的哪一部分。 因此，向量在概念上被划分为子向量，各个VU并行地在各个子向量上执行指令。 然后，每个VU可以按照预期的方式执行指令，但只能在整个向量的子部分上执行。 这允许在n路VU上写入用于执行的指令由多个n路VU执行，每个N个VU从矢量的不同点开始，使得指令可以在多于n个VU的数据项上执行 矢量并行。