公开(公告)号：US11961175B2

公开(公告)日：2024-04-16

申请号：US17874019

申请日：2022-07-26

Applicant: Imagination Technologies Limited

Inventor： Rostam King ,  Kenneth Rovers

IPC: G06T15/04 ,  G06F17/18 ,  G06T7/60 ,  G06T15/50

CPC classification number: G06T15/04 ,  G06F17/18 ,  G06T7/60 ,  G06T15/503

Abstract: A method of performing anisotropic texture filtering includes generating one or more parameters describing an elliptical footprint in texture space; performing isotropic filtering at each of a plurality of sampling points along a major axis of the elliptical footprint, wherein a spacing between adjacent sampling points of the plurality of sampling points is proportional to √{square root over (1−η−2)} units, wherein η is a ratio of a major radius of an ellipse to be sampled and a minor radius of the ellipse to be sampled, wherein the ellipse to be sampled is based on the elliptical footprint; and combining results of the isotropic filtering at the plurality of sampling points with a Gaussian filter to generate at least a portion of a filter result.

公开(公告)号：US20230409287A1

公开(公告)日：2023-12-21

申请号：US18129019

申请日：2023-03-30

Applicant: Imagination Technologies Limited

Inventor： Kenneth Rovers ,  Faizan Nazar

IPC: G06F7/50 ,  G06F7/523 ,  G06F5/01

CPC classification number: G06F7/50 ,  G06F7/523 ,  G06F5/01

Abstract: Accumulator hardware logic includes first and second addition logic units and a store. The first addition logic unit comprises a first input, a second input and an output, each of the first and second inputs arranged to receive an input value in each clock cycle. The second addition logic unit comprises a first input that is connected directly to the output of the first addition logic unit. It also comprises a second input and an output. The store is arranged to store a result output by the second addition logic unit. The accumulator hardware logic further comprises shifting hardware and/or negation hardware positioned in a feedback path between the store and the second input of the second addition logic unit. The shifting hardware is configured to perform a shift by a fixed number of bit positions in a fixed direction.

公开(公告)号：US20210132902A1

公开(公告)日：2021-05-06

申请号：US17141284

申请日：2021-01-05

Applicant: Imagination Technologies Limited

Inventor： Kenneth Rovers

IPC: G06F5/01 ,  H03M7/24 ,  G06F7/48

Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1),bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

公开(公告)号：US10884702B2

公开(公告)日：2021-01-05

申请号：US16876402

申请日：2020-05-18

Applicant: Imagination Technologies Limited

Inventor： Kenneth Rovers

IPC: G06F5/01 ,  G06F7/48 ,  H03M7/24

Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min {(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

公开(公告)号：US20200142668A1

公开(公告)日：2020-05-07

申请号：US16734317

申请日：2020-01-04

Applicant: Imagination Technologies Limited

Inventor： Kenneth Rovers

IPC: G06F5/01 ,  G06F7/48 ,  H03M7/24

Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew−1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew −1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

公开(公告)号：US10558428B2

公开(公告)日：2020-02-11

申请号：US15935313

申请日：2018-03-26

Applicant: Imagination Technologies Limited

Inventor： Kenneth Rovers

IPC: G06F5/01 ,  H03M7/24 ,  G06F7/48

Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a first shifter operable to receive a first significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a first output, wherein min{(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number; an inverting unit configured to invert the bit values of the exponent; a second shifter coupled to the inverting unit configured to receive a second significand input comprising a contiguous set of the most significant bits of the significand and configured to right-shift the input by a number of bits equal to the value represented by the p least significant bits of the inverted exponent to generate a second output, wherein min{(ew−1), bitwidth(fw)}≤p≤(ew−1); and a multiplexer coupled to the first and second shifters and configured to: receive a first input comprising a contiguous set of bits of the first output and a second input comprising a contiguous set of bits of the second output; and output the first input if the most significant bit of the exponent is equal to one; and output the second input if the most significant bit of the exponent is equal to zero.

公开(公告)号：US20250165219A1

公开(公告)日：2025-05-22

申请号：US18933060

申请日：2024-10-31

Applicant: Imagination Technologies Limited

Inventor： Kenneth Rovers ,  Max Freiburghaus ,  Thomas Ferrere

IPC: G06F7/499

Abstract: A method of rounding a floating-point number in an Extended Exponent Range (EER), that would be a denormal floating-point number represented in an Unextended Exponent Range (UER) includes the steps of receiving, at an arithmetic unit, a plurality of input numbers in the EER representation, each input number comprising a sign bit (si), exponent bits (ei) and mantissa bits (mi); performing an arithmetic operation to produce an output number in the EER representation comprising a sign bit (sa), an exponent bits (ea) and mantissa bits (ma); constructing a rounding mask based on the exponent bits (ea) computed by the arithmetic operation; and applying the rounding mask to the output number in the EER representation to round the output number to correct position as if rounding in the UER representation.

公开(公告)号：US12229002B2

公开(公告)日：2025-02-18

申请号：US18193446

申请日：2023-03-30

Applicant: Imagination Technologies Limited

Inventor： Faizan Nazar ,  Kenneth Rovers

IPC: G06F11/10 ,  G01R31/317

Abstract: An error detection circuit and a method for performing a cyclic redundancy check on a clock gated register signal are disclosed. The error detection circuit comprising a first register, a check bit processing logic and an error detection module. The first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal. The check bit processing logic configured to, in response to a control signal, update a second register with a check bit, wherein the control signal (b) is the same as the clock enabling signal. The error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.

公开(公告)号：US20230384375A1

公开(公告)日：2023-11-30

申请号：US18193509

申请日：2023-03-30

Applicant: Imagination Technologies Limited

Inventor： Faizan Nazar ,  Kenneth Rovers

IPC: G01R31/317

CPC classification number: G01R31/31727

Abstract: An error detection circuit and method for performing cyclic redundancy check on a clock gated register signal is disclosed. The error detection circuit comprise a first register, a second register, a third register and an error detection module. The first register is a clock gated register and is configured to be updated with a data signal (x) in response to a clock enabling signal. The second register is configured to be updated with a check bit (c) based on the data signal (x). The check bit is calculated by a check bit calculation unit. The third register is configured to be updated with a current value (b) of the clock enabling signal. The error detection module is configured for calculating an indication bit (I) based on at least the output of the first register, the output of the second register and the output of the third register.

公开(公告)号：US20230384374A1

公开(公告)日：2023-11-30

申请号：US18193446

申请日：2023-03-30

Applicant: Imagination Technologies Limited

Inventor： Faizan Nazar ,  Kenneth Rovers

IPC: G01R31/317

CPC classification number: G01R31/31727

Abstract: An error detection circuit and a method for performing a cyclic redundancy check on a clock gated register signal are disclosed. The error detection circuit comprising a first register, a check bit processing logic and an error detection module. The first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal. The check bit processing logic configured to, in response to a control signal, update a second register with a check bit, wherein the control signal (b) is the same as the clock enabling signal. The error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.