公开(公告)号：US20250054097A1

公开(公告)日：2025-02-13

申请号：US18929703

申请日：2024-10-29

Applicant: Imagination Technologies Limited

Inventor： Roger Hernando Buch ,  Panagiotis Velentzas ,  Richard Broadhurst ,  Xile Yang ,  John W. Howson

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06F12/02 ,  G06T1/60

Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.

公开(公告)号：US12131403B2

公开(公告)日：2024-10-29

申请号：US18231126

申请日：2023-08-07

Applicant: Imagination Technologies Limited

Inventor： Roger Hernando Buch ,  Panagiotis Velentzas ,  Richard Broadhurst ,  Xile Yang ,  John W. Howson

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06F12/02 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/52 ,  G06F12/0261 ,  G06T1/60

Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.

公开(公告)号：US12100062B2

公开(公告)日：2024-09-24

申请号：US17737118

申请日：2022-05-05

Applicant: Imagination Technologies Limited

Inventor： John W. Howson ,  Richard Broadhurst ,  Steven Fishwick

IPC: G06T1/20 ,  G06F9/38 ,  G06T1/60 ,  G06T7/11 ,  G06T11/40 ,  G06T15/00 ,  H04N19/00 ,  H04N19/115 ,  H04N19/117 ,  H04N19/124 ,  H04N19/14 ,  H04N19/174

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06T1/60 ,  G06T7/11 ,  G06T11/40 ,  G06T15/005 ,  H04N19/00 ,  H04N19/115 ,  H04N19/117 ,  H04N19/124 ,  H04N19/14 ,  H04N19/174

Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.

公开(公告)号：US20230418668A1

公开(公告)日：2023-12-28

申请号：US18244655

申请日：2023-09-11

Applicant: Imagination Technologies Limited

Inventor： Isuru Herath ,  Richard Broadhurst

IPC: G06F9/48 ,  G06F9/38 ,  G06T1/20

CPC classification number: G06F9/4881 ,  G06F9/3836 ,  G06F9/3885 ,  G06T1/20

Abstract: A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.

公开(公告)号：US20220405998A1

公开(公告)日：2022-12-22

申请号：US17680947

申请日：2022-02-25

Applicant: Imagination Technologies Limited

Inventor： Panagiotis Velentzas ,  John W. Howson ,  Richard Broadhurst

IPC: G06T15/00 ,  G06F9/50

Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.

公开(公告)号：US11422742B2

公开(公告)日：2022-08-23

申请号：US16791433

申请日：2020-02-14

Applicant: Imagination Technologies Limited

Inventor： Isuru Herath ,  Richard Broadhurst

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/50

Abstract: Methods of memory allocation map registers referenced by different groups of instances of the same task to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.

公开(公告)号：US20220261950A1

公开(公告)日：2022-08-18

申请号：US17737118

申请日：2022-05-05

Applicant: Imagination Technologies Limited

Inventor： John W. Howson ,  Richard Broadhurst ,  Steven Fishwick

IPC: G06T1/20 ,  G06T1/60 ,  G06T7/11 ,  H04N19/115 ,  H04N19/117 ,  H04N19/124 ,  H04N19/14 ,  H04N19/174 ,  G06F9/38 ,  G06T11/40 ,  G06T15/00 ,  H04N19/00

Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.

公开(公告)号：US20210110509A1

公开(公告)日：2021-04-15

申请号：US17130321

申请日：2020-12-22

Applicant: Imagination Technologies Limited

Inventor： John W. Howson ,  Richard Broadhurst ,  Steven Fishwick

IPC: G06T1/20 ,  G06T1/60 ,  G06T7/11 ,  H04N19/115 ,  H04N19/117 ,  H04N19/124 ,  H04N19/14 ,  H04N19/174 ,  G06F9/38 ,  G06T11/40 ,  G06T15/00 ,  H04N19/00

Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.

公开(公告)号：US20200082606A1

公开(公告)日：2020-03-12

申请号：US16683085

申请日：2019-11-13

Applicant: Imagination Technologies Limited

Inventor： Richard Broadhurst ,  John Howson ,  Robert Theed

IPC: G06T15/40 ,  G06T15/00

Abstract: A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitives, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will subsequently be hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.

公开(公告)号：US10565772B2

公开(公告)日：2020-02-18

申请号：US15868556

申请日：2018-01-11

Applicant: Imagination Technologies Limited

Inventor： John W. Howson ,  Richard Broadhurst ,  Steven Fishwick

IPC: G06T15/00 ,  G06T17/10 ,  G06T15/40 ,  G06T15/04 ,  G06T15/06 ,  G06T15/80

Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.