公开(公告)号：US10211200B2

公开(公告)日：2019-02-19

申请号：US15883591

申请日：2018-01-30

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Mayank Shrivastava ,  Milova Paul ,  Christian Russ ,  Harald Gossner

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/78

Abstract: The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.

公开(公告)号：US11522078B2

公开(公告)日：2022-12-06

申请号：US16629156

申请日：2018-07-06

Applicant: Indian Institute of Science

Inventor： Rohith Soman ,  Ankit Soni ,  Mayank Shrivastava ,  Srinivasan Raghavan ,  Navakant Bhat

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423

Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.

公开(公告)号：US11031493B2

公开(公告)日：2021-06-08

申请号：US16431151

申请日：2019-06-04

Applicant: Indian Institute of Science

Inventor： Mayank Shrivastava ,  Vipin Joshi

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: The present invention proposes a set of impurity doping configurations for GaN buffer in an AlGaN/GaN HEMT device to improve breakdown characteristics of the device. The breakdown characteristics depend on a unique mix of donor and acceptor traps and using carbon as a dopant increases both donor and acceptor trap concentrations, resulting in a trade-off in breakdown voltage improvement and device performance. A modified silicon and carbon co-doping is proposed, which enables independent control over donor and acceptor trap concentrations in the buffer, thus potentially improving breakdown characteristics of the device without adversely affecting the device performance.

公开(公告)号：US10483258B2

公开(公告)日：2019-11-19

申请号：US15899117

申请日：2018-02-19

Applicant: Indian Institute of Science

Inventor： Mayank Shrivastava ,  Milova Paul ,  Harald Gossner

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/78 ,  H01L29/74 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/06

Abstract: The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided. The present disclosure also provides a hybrid contact and junction profile scheme where ESD protection element(s) have fins that are partially silicided with or without deep junctions depending on their application, and functional devices have fins that are fully silicided with the silicide edge crossing the junction. On the other hand, a dual Epi scheme is implemented such that ESD protection elements have fins with Epi contact, and functional devices have fins that are fully silicided without Epi (raised S/D) contact.

公开(公告)号：US20180248025A1

公开(公告)日：2018-08-30

申请号：US15899102

申请日：2018-02-19

Applicant: Indian Institute of Science

Inventor： Mayank Shrivastava ,  Milova Paul ,  Harald Gossner

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: SCRs are a must for ESD protection in low voltage—high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

公开(公告)号：US20180247929A1

公开(公告)日：2018-08-30

申请号：US15899117

申请日：2018-02-19

Applicant: Indian Institute of Science

Inventor： Mayank Shrivastava ,  Milova Paul ,  Harald Gossner

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/74 ,  H01L21/8234

Abstract: The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided. The present disclosure also provides a hybrid contact and junction profile scheme where ESD protection element(s) have fins that are partially silicided with or without deep junctions depending on their application, and functional devices have fins that are fully silicided with the silicide edge crossing the junction. On the other hand, a dual Epi scheme is implemented such that ESD protection elements have fins with Epi contact, and functional devices have fins that are fully silicided without Epi (raised S/D) contact.

公开(公告)号：US10553712B2

公开(公告)日：2020-02-04

申请号：US16032502

申请日：2018-07-11

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Mayank Shrivastava

IPC: H01L29/739 ,  H01L29/778 ,  H01L21/768 ,  H01L29/06 ,  H01L23/31 ,  H01L29/20

Abstract: The present disclosure provides a superjunction based design for normally-OFF HEMT that has two key components: (i) a recessed high-K metal gate and (ii) a superjunction layer under the gate, which is embedded within the N-type GaN buffer layers and separated from recessed gate. Recess gate is to deplete the 2 DEG from the channel region (under the gate) when the transistor is under OFF state. The present disclosure provides a new, improved, efficient and technically advanced HEMT device which can provide higher breakdown voltage, when compared to designs available in the prior-art, without affecting the performance figure of merits. Further, the new HEMT device offers improved breakdown voltage as compared to ON-resistance trade-off, improved the short channel effects, improved gate control over channel, improved switching speed for a given breakdown voltage, and improved device reliability. Furthermore, the new HEMT device lowers gate-to-drain (miller) capacitance and is available at low cost.

公开(公告)号：US10535762B2

公开(公告)日：2020-01-14

申请号：US15899102

申请日：2018-02-19

Applicant: Indian Institute of Science

Inventor： Mayank Shrivastava ,  Milova Paul ,  Harald Gossner

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285

Abstract: SCRs are a must for ESD protection in low voltage—high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

公开(公告)号：US10319662B2

公开(公告)日：2019-06-11

申请号：US15883749

申请日：2018-01-30

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Mayank Shrivastava ,  Milova Paul ,  Christian Russ ,  Harald Gossner

IPC: H01L23/367 ,  H01L27/088 ,  H01L29/423 ,  H01L29/74 ,  H01L29/861 ,  H01L29/06 ,  H01L27/02 ,  H01L29/735

Abstract: The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.

公开(公告)号：US20190067440A1

公开(公告)日：2019-02-28

申请号：US16114650

申请日：2018-08-28

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Mayank Shrivastava ,  Sayak Dutta Gupta ,  Ankit Soni ,  Srinivasan Raghavan ,  Navakanta Bhat

IPC: H01L29/49 ,  H01L29/778 ,  H01L21/02

Abstract: The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlxTi1-xO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlxTi1-xO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlxTi1-xO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, Ron=8.9 Ωmm, interface trap density