公开(公告)号：US12154886B2

公开(公告)日：2024-11-26

申请号：US17502163

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L23/02 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.

公开(公告)号：US20240113026A1

公开(公告)日：2024-04-04

申请号：US18526127

申请日：2023-12-01

Applicant: Infineon Technologies AG

Inventor： Edward Fürgut ,  Ravi Keshav Joshi ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L23/53238 ,  H01L21/7685 ,  H01L24/45 ,  H01L29/1608 ,  H01L29/45 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/05181 ,  H01L2224/05672 ,  H01L2224/05679 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.

公开(公告)号：US11862582B2

公开(公告)日：2024-01-02

申请号：US17502084

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Bemmerl ,  Martin Gruber ,  Martin Richard Niessner

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/564 ,  H01L21/481 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49541 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.

公开(公告)号：US11515244B2

公开(公告)日：2022-11-29

申请号：US16748049

申请日：2020-01-21

Applicant: Infineon Technologies AG

Inventor： Bun Kian Tay ,  Mei Yih Goh ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Thorsten Scharf ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US11264356B2

公开(公告)日：2022-03-01

申请号：US16842417

申请日：2020-04-07

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Andreas Grassmann ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.

公开(公告)号：US20200273790A1

公开(公告)日：2020-08-27

申请号：US16748049

申请日：2020-01-21

Applicant: Infineon Technologies AG

Inventor： Bun Kian Tay ,  Mei Yih Goh ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Thorsten Scharf ,  Chee Voon Tan

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US10096584B2

公开(公告)日：2018-10-09

申请号：US15337733

申请日：2016-10-28

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Guido Boenig ,  Irmgard Escher-Poeppel ,  Edward Fuergut ,  Martin Gruber ,  Thorsten Meyer

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/50 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L21/60

Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.

公开(公告)号：US10037972B2

公开(公告)日：2018-07-31

申请号：US15137062

申请日：2016-04-25

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Martin Gruber ,  Wolfram Hable

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/31 ,  H01L23/473 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L23/40

Abstract: Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material.

公开(公告)号：US20170125395A1

公开(公告)日：2017-05-04

申请号：US15337733

申请日：2016-10-28

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Guido Boenig ,  Irmgard Escher-Poeppel ,  Edward Fuergut ,  Martin Gruber ,  Thorsten Meyer

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/14 ,  H01L21/50 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L23/142 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/072 ,  H01L2021/60015 ,  H01L2021/60022 ,  H01L2021/60277 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/214 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10344 ,  H01L2924/1301 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2224/85399

Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.

公开(公告)号：US09564578B2

公开(公告)日：2017-02-07

申请号：US14947649

申请日：2015-11-20

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Martin Gruber ,  Rainer Markus Schaller ,  Franz Jost ,  Stefan Mieslinger ,  Liu Chen ,  Toni Salminen ,  Giuliano Angelo Babulano ,  Jens Oetjen ,  Markus Dinkel

IPC: H01L25/16 ,  H01L43/02 ,  H01L43/06 ,  H01L43/08 ,  G01R33/07 ,  G01R33/09

CPC classification number: H01L43/02 ,  G01R33/07 ,  G01R33/09 ,  H01L27/22 ,  H01L43/065 ,  H01L43/08 ,  H01L2224/0603 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40 ,  H01L2224/48137 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014

Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.

Abstract translation: 半导体封装包括附接到衬底的半导体管芯和作为与半导体管芯相同的半导体封装的一部分的磁场传感器，并且位于靠近半导体管芯的电流通路的位置，使得磁场传感器可感测 电流在电流通路中流动产生的磁场。 磁场传感器包括与电流通路电隔离的第一磁场感测部件，并被定位成使得在电流通路中流动的电流产生的磁场沿第一方向冲击第一磁场感测部件。 磁场传感器还包括与电流路径电隔离并定位成使得磁场在不同于第一方向的第二方向上撞击在第二磁场感测部件上的第二磁场感测部件。