公开(公告)号：US09941276B2

公开(公告)日：2018-04-10

申请号：US15197930

申请日：2016-06-30

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Norbert Krischke

IPC: H01L27/07 ,  H01L29/08 ,  H01L21/74 ,  H01L49/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L21/321 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L27/0733 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/32105 ,  H01L21/743 ,  H01L21/823437 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7825 ,  H01L29/945

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

公开(公告)号：US09355909B2

公开(公告)日：2016-05-31

申请号：US14148776

申请日：2014-01-07

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Stefan Decker ,  Norbert Krischke ,  Christoph Kadow

IPC: H01L27/148 ,  H01L29/768 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/105 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66537 ,  H01L29/78

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract translation: 一种具有场效应晶体管和制造方法的集成电路。 一个实施例提供了包括第一FET和第二FET的集成电路。 第一FET的源极，漏极，栅极中的至少一个电连接到第二FET的源极，漏极，栅极中的相应一个栅极。 第一FET的源极，漏极，栅极以及第二FET的源极，漏极，栅极之间的至少另外的栅极分别连接到电路元件。 沿着第一和第二FET中的每一个的通道的主体的掺杂剂浓度在通道内的峰值位置处具有峰值。

公开(公告)号：US20150008498A1

公开(公告)日：2015-01-08

申请号：US14330847

申请日：2014-07-14

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Norbert Krischke

IPC: H01L27/07 ,  H01L21/321 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L49/02

CPC classification number: H01L27/0733 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/32105 ,  H01L21/743 ,  H01L21/823437 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7825 ,  H01L29/945

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Abstract translation: 半导体元件布置方法包括产生沟槽晶体管结构，其包括设置在半导体本体中的至少一个沟槽和设置在至少一个沟槽中的至少一个栅电极。 该方法还包括制造电容器结构，其包括设置在至少一个另外的沟槽中的电极结构，所述电极结构包括至少一个电极。 电极结构的栅电极和至少一个电极通过常规工艺步骤制造。

公开(公告)号：US20140120673A1

公开(公告)日：2014-05-01

申请号：US14148776

申请日：2014-01-07

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Stefan Decker ,  Norbert Krischke ,  Christoph Kadow

IPC: H01L21/8234

CPC classification number: H01L29/105 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66537 ,  H01L29/78

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract translation: 一种具有场效应晶体管和制造方法的集成电路。 一个实施例提供了包括第一FET和第二FET的集成电路。 第一FET的源极，漏极，栅极中的至少一个电连接到第二FET的源极，漏极，栅极中的相应一个栅极。 第一FET的源极，漏极，栅极以及第二FET的源极，漏极，栅极之间的至少另外的栅极分别连接到电路元件。 沿着第一和第二FET中的每一个的通道的主体的掺杂剂浓度在通道内的峰值位置处具有峰值。

公开(公告)号：US09735264B2

公开(公告)日：2017-08-15

申请号：US14840925

申请日：2015-08-31

Applicant: Infineon Technologies AG

Inventor： Norbert Krischke ,  Bernhard Auer ,  Robert Illing

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/7803 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7815

Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

公开(公告)号：US09397091B2

公开(公告)日：2016-07-19

申请号：US14330847

申请日：2014-07-14

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Norbert Krischke

IPC: H01L27/06 ,  H01L27/07 ,  H01L21/74 ,  H01L49/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L21/321 ,  H01L29/06

CPC classification number: H01L27/0733 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/32105 ,  H01L21/743 ,  H01L21/823437 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7825 ,  H01L29/945

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Abstract translation: 半导体元件布置方法包括产生沟槽晶体管结构，其包括设置在半导体本体中的至少一个沟槽和设置在至少一个沟槽中的至少一个栅电极。 该方法还包括制造电容器结构，其包括设置在至少一个另外的沟槽中的电极结构，所述电极结构包括至少一个电极。 电极结构的栅电极和至少一个电极通过常规工艺步骤制造。

公开(公告)号：US09761665B2

公开(公告)日：2017-09-12

申请号：US15157448

申请日：2016-05-18

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Stefan Decker ,  Norbert Krischke ,  Christoph Kadow

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/105 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66537 ,  H01L29/78

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

公开(公告)号：US20170309739A1

公开(公告)日：2017-10-26

申请号：US15646496

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Norbert Krischke ,  Bernhard Auer ,  Robert Illing

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L29/7803 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7815

Abstract: A semiconductor device includes at least one wiring layer disposed on a semiconductor body, a field effect transistor integrated in the semiconductor body, the field effect transistor having a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body, a first circuit integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit integrated in the semiconductor body and remote from the first circuit. The semiconductor device further includes a first additional trench formed in the semiconductor body and at least one conductive pad formed in the at least one wiring layer. The first additional trench includes at least one connecting line which electrically connects the first circuit and the second circuit. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

公开(公告)号：US20160307889A1

公开(公告)日：2016-10-20

申请号：US15197930

申请日：2016-06-30

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Norbert Krischke

IPC: H01L27/07 ,  H01L29/66 ,  H01L49/02 ,  H01L29/40 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/0733 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/32105 ,  H01L21/743 ,  H01L21/823437 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7825 ,  H01L29/945

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

公开(公告)号：US20160071972A1

公开(公告)日：2016-03-10

申请号：US14840925

申请日：2015-08-31

Applicant: Infineon Technologies AG

Inventor： Norbert Krischke ,  Bernhard Auer ,  Robert Illing

IPC: H01L29/78

CPC classification number: H01L29/7803 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7815

Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

Abstract translation: 半导体器件包括半导体本体，设置在半导体本体上的至少一个布线层和集成在半导体本体中的场效应晶体管。 场效应晶体管具有驻留在半导体本体中形成的相应栅极沟槽中的多个栅电极。 第一电路集成在与场效应晶体管相邻的半导体本体中，并且第二电路集成在远离第一电路的半导体本体中。 第一附加沟槽形成在半导体本体中，并且包括至少一个电连接第一电路和第二电路的连接线。 半导体器件还包括形成在至少一个布线层中的至少一个导电焊盘。 所述至少一个导电垫被布置成至少部分地覆盖所述第一附加沟槽以形成所述至少一个连接线的屏蔽。