公开(公告)号：US10776293B2

公开(公告)日：2020-09-15

申请号：US15967823

申请日：2018-05-01

Applicant: Integrated Device Technology, Inc.

Inventor： Shwetal Arvind Patel ,  Andy Zhang ,  Wen Jie Meng ,  Chenxiao Ren ,  Alejandro F. Gonzalez

IPC: G06F3/00 ,  G06F13/16 ,  G06F3/06 ,  G06F1/10

Abstract: An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.

公开(公告)号：US20190340142A1

公开(公告)日：2019-11-07

申请号：US15968111

申请日：2018-05-01

Applicant: Integrated Device Technology, Inc.

Inventor： Shwetal Arvind Patel ,  Andy Zhang ,  Wen Jie Meng ,  Chenxiao Ren ,  Alejandro F. Gonzalez

IPC: G06F13/16 ,  G06F13/24 ,  G06F3/06 ,  G06F1/10

Abstract: An apparatus including a host interface and a power management interface. The host interface may be configured to receive control words from a host. The power management interface may be configured to (i) enable the host to read/write data from/to a power management circuit of a dual in-line memory module, (ii) communicate the data, (iii) generate a clock signal and (iv) communicate an interrupt signal. The power management interface is disabled at power on. The apparatus is configured to (i) decode the control words, (ii) enable the power management interface when the control words provide an enable command and (iii) perform a response to the interrupt signal. The clock signal may operate independently from a host clock.

公开(公告)号：US10769082B2

公开(公告)日：2020-09-08

申请号：US15968111

申请日：2018-05-01

Applicant: Integrated Device Technology, Inc.

Inventor： Shwetal Arvind Patel ,  Andy Zhang ,  Wen Jie Meng ,  Chenxiao Ren ,  Alejandro F. Gonzalez

IPC: G06F3/00 ,  G06F13/16 ,  G06F13/24 ,  G06F3/06 ,  G06F1/10

Abstract: An apparatus including a host interface and a power management interface. The host interface may be configured to receive control words from a host. The power management interface may be configured to (i) enable the host to read/write data from/to a power management circuit of a dual in-line memory module, (ii) communicate the data, (iii) generate a clock signal and (iv) communicate an interrupt signal. The power management interface is disabled at power on. The apparatus is configured to (i) decode the control words, (ii) enable the power management interface when the control words provide an enable command and (iii) perform a response to the interrupt signal. The clock signal may operate independently from a host clock.

公开(公告)号：US20190340141A1

公开(公告)日：2019-11-07

申请号：US15967823

申请日：2018-05-01

Applicant: Integrated Device Technology, Inc.

Inventor： Shwetal Arvind Patel ,  Andy Zhang ,  Wen Jie Meng ,  Chenxiao Ren ,  Alejandro F. Gonzalez

IPC: G06F13/16 ,  G06F3/06 ,  G06F1/10

Abstract: An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.