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公开(公告)号：US10776293B2
公开(公告)日：2020-09-15
申请号：US15967823
申请日：2018-05-01
Applicant: Integrated Device Technology, Inc.
Inventor： Shwetal Arvind Patel , Andy Zhang , Wen Jie Meng , Chenxiao Ren , Alejandro F. Gonzalez
Abstract: An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.
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公开(公告)号：US10200050B1
公开(公告)日：2019-02-05
申请号：US15904320
申请日：2018-02-24
Applicant: Integrated Device Technology, Inc.
Inventor： Chenxiao Ren
Abstract: An apparatus including a first circuit and a second circuit. The first circuit may generate an output signal with a regulated voltage and maintain a constant switch frequency having a first on time and a first off time. The second circuit may generate a shifted signal based on a phase delay with respect to the output signal and maintain a shifted frequency having a second on time and a second off time. The second on time may follow the first on time by the phase delay. The second on time may be based on the first on time and transient conditions of a load. The apparatus may implement an automatic phase shift adjustment. A current sensing comparison may implement a cycle-by-cycle comparison between the output signal and the shifted signal to determine the second on time and perform a tuning operation to achieve inductor current balancing.
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公开(公告)号：US10769082B2
公开(公告)日：2020-09-08
申请号：US15968111
申请日：2018-05-01
Applicant: Integrated Device Technology, Inc.
Inventor： Shwetal Arvind Patel , Andy Zhang , Wen Jie Meng , Chenxiao Ren , Alejandro F. Gonzalez
Abstract: An apparatus including a host interface and a power management interface. The host interface may be configured to receive control words from a host. The power management interface may be configured to (i) enable the host to read/write data from/to a power management circuit of a dual in-line memory module, (ii) communicate the data, (iii) generate a clock signal and (iv) communicate an interrupt signal. The power management interface is disabled at power on. The apparatus is configured to (i) decode the control words, (ii) enable the power management interface when the control words provide an enable command and (iii) perform a response to the interrupt signal. The clock signal may operate independently from a host clock.
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公开(公告)号：US10425093B2
公开(公告)日：2019-09-24
申请号：US16216365
申请日：2018-12-11
Applicant: Integrated Device Technology, Inc.
Inventor： Chenxiao Ren
Abstract: An apparatus including a first circuit and a second circuit. The first circuit may generate an output signal with a regulated voltage and maintain a constant switch frequency having a first on time and a first off time. The second circuit may generate a shifted signal based on a phase delay with respect to the output signal and maintain a shifted frequency having a second on time and a second off time. The second on time may follow the first on time by the phase delay. The second on time may be based on the first on time and transient conditions of a load. The apparatus may implement an automatic phase shift adjustment. A current sensing comparison may implement a cycle-by-cycle comparison between the output signal and the shifted signal to determine the second on time and perform a tuning operation to achieve inductor current balancing.
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5.发明授权公开(公告)号：US10241538B2
公开(公告)日：2019-03-26
申请号：US15439190
申请日：2017-02-22
Applicant: Integrated Device Technology, Inc.
Inventor： David Chang , Xudong Shi , Shubing Zhai , Chenxiao Ren
Abstract: An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.
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Patent Agency Ranking
公开(公告)号：US11249539B2
公开(公告)日：2022-02-15
申请号：US16724857
申请日：2019-12-23
Applicant: Integrated Device Technology, Inc.
Inventor： Shwetal Arvind Patel , Chenxiao Ren
IPC: G06F1/32 , G06F1/3234
Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.
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公开(公告)号：US20190340141A1
公开(公告)日：2019-11-07
申请号：US15967823
申请日：2018-05-01
Applicant: Integrated Device Technology, Inc.
Inventor： Shwetal Arvind Patel , Andy Zhang , Wen Jie Meng , Chenxiao Ren , Alejandro F. Gonzalez
Abstract: An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.
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公开(公告)号：US20190340142A1
公开(公告)日：2019-11-07
申请号：US15968111
申请日：2018-05-01
Applicant: Integrated Device Technology, Inc.
Inventor： Shwetal Arvind Patel , Andy Zhang , Wen Jie Meng , Chenxiao Ren , Alejandro F. Gonzalez
Abstract: An apparatus including a host interface and a power management interface. The host interface may be configured to receive control words from a host. The power management interface may be configured to (i) enable the host to read/write data from/to a power management circuit of a dual in-line memory module, (ii) communicate the data, (iii) generate a clock signal and (iv) communicate an interrupt signal. The power management interface is disabled at power on. The apparatus is configured to (i) decode the control words, (ii) enable the power management interface when the control words provide an enable command and (iii) perform a response to the interrupt signal. The clock signal may operate independently from a host clock.
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9.发明申请公开(公告)号：US20190268011A1
公开(公告)日：2019-08-29
申请号：US16216365
申请日：2018-12-11
Applicant: Integrated Device Technology, Inc.
Inventor： Chenxiao Ren
Abstract: An apparatus including a first circuit and a second circuit. The first circuit may generate an output signal with a regulated voltage and maintain a constant switch frequency having a first on time and a first off time. The second circuit may generate a shifted signal based on a phase delay with respect to the output signal and maintain a shifted frequency having a second on time and a second off time. The second on time may follow the first on time by the phase delay. The second on time may be based on the first on time and transient conditions of a load. The apparatus may implement an automatic phase shift adjustment. A current sensing comparison may implement a cycle-by-cycle comparison between the output signal and the shifted signal to determine the second on time and perform a tuning operation to achieve inductor current balancing.
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公开(公告)号：US20180275714A1
公开(公告)日：2018-09-27
申请号：US15468310
申请日：2017-03-24
Applicant: Integrated Device Technology, Inc.
Inventor： David Chang , Xudong Shi , Shubing Zhai , Chenxiao Ren
CPC classification number: G06F13/4072 , G06F13/1689 , G06F13/4291
Abstract: An apparatus comprising an input interface an output interface and a coupling interface. The input interface may comprise a plurality of input stages each configured to (i) receive a data signal and a coupled clock signal and (ii) present an intermediate signal. The output interface may comprise a plurality of output stages each configured to (i) receive the intermediate signal from one of the input stages, (ii) receive the coupled clock signal and (iii) present an output signal. The coupling interface may be configured to (i) receive the clock signal and (ii) present the coupled clock signal to each of (a) the input stages and (b) the output stages. The coupling interface may generate a plurality of inductive couples and (b) the inductive couples may enable a synchronization of the coupled clock signal with the clock signal for each of the input stages and the output stages.
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