公开(公告)号：US10671300B1

公开(公告)日：2020-06-02

申请号：US16258972

申请日：2019-01-28

Applicant: Integrated Device Technology, Inc.

Inventor： Craig DeSimone ,  Praveen Singh ,  Alejandro Gonzalez ,  Yue Yu ,  YanBo Wang

IPC: G06F3/06 ,  G11C11/4096 ,  G11C11/4093

Abstract: A method for responding to a command sequence includes receiving a signal from a host carrying a plurality of commands in the command sequence, detecting a non-consecutive clock associated with a start of a current command in the command sequence, and generating a control signal in an active state to indicate detection of the non-consecutive clock.

公开(公告)号：US10236870B2

公开(公告)日：2019-03-19

申请号：US15834547

申请日：2017-12-07

Applicant: Integrated Device Technology, Inc.

Inventor： Zhigang Hu ,  Hui Yu ,  Shaokang Wang ,  Yuan Zhang ,  Yue Yu

IPC: G11C5/04 ,  G11C7/10 ,  H03K5/15

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal. At least two of the respective delays may have a different duration. The first circuit may also be configured to change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.

公开(公告)号：US20170256303A1

公开(公告)日：2017-09-07

申请号：US15059609

申请日：2016-03-03

Applicant: Integrated Device Technology, Inc.

Inventor： Yue Yu ,  Craig DeSimone ,  Al Xuefeng Fang ,  Yanbo Wang

IPC: G11C11/4094 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  G11C5/04 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

公开(公告)号：US20170212847A1

公开(公告)日：2017-07-27

申请号：US15480616

申请日：2017-04-06

Applicant: Integrated Device Technology, Inc.

Inventor： Yanbo Wang ,  Praveen Rajan Singh ,  Yue Yu ,  Craig DeSimone

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/12 ,  G06F13/40 ,  G11C7/22

CPC classification number: G11C11/4093 ,  G06F13/4068 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4076 ,  H04L25/028 ,  H04L25/0286

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.

公开(公告)号：US10304520B1

公开(公告)日：2019-05-28

申请号：US15886955

申请日：2018-02-02

Applicant: Integrated Device Technology, Inc.

Inventor： Yi Xie ,  Yue Yu

IPC: G11C5/14 ,  G11C11/4093 ,  G11C11/4074

Abstract: An apparatus includes a line-termination circuit and a continuous-time linear equalizer circuit. The line-termination circuit may be configured to generate a data signal in response to an input signal. The input signal generally resides in a first voltage domain. The input signal may be single-ended. The data signal may be generated in the first voltage domain. The continuous-time linear equalizer circuit may be configured to generate an intermediate signal by equalizing the data signal relative to a reference voltage. The continuous-time linear equalizer circuit generally operates in a second voltage domain. The first voltage domain may be higher than the second voltage domain.

公开(公告)号：US09853632B2

公开(公告)日：2017-12-26

申请号：US15000214

申请日：2016-01-19

Applicant: Integrated Device Technology, Inc.

Inventor： Zhigang Hu ,  Hui Yu ,  Shaokang Wang ,  Yuan Zhang ,  Yue Yu

IPC: H03K5/04 ,  H03K7/08 ,  H03K5/15 ,  G11C7/10

CPC classification number: H03K5/15 ,  G11C5/04 ,  G11C7/1057

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal and (ii) change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.

公开(公告)号：US09794087B2

公开(公告)日：2017-10-17

申请号：US15059609

申请日：2016-03-03

Applicant: Integrated Device Technology, Inc.

Inventor： Yue Yu ,  Craig DeSimone ,  Al Xuefeng Fang ,  Yanbo Wang

IPC: H04L25/02 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4093 ,  G06F13/40

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  G11C5/04 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

公开(公告)号：US09653147B1

公开(公告)日：2017-05-16

申请号：US14956955

申请日：2015-12-02

Applicant: Integrated Device Technology, Inc.

Inventor： Yanbo Wang ,  Praveen Rajan Singh ,  Yue Yu ,  Craig DeSimone

IPC: G11C11/4093 ,  G11C11/4076 ,  H04L25/02

CPC classification number: G11C11/4093 ,  G06F13/4068 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4076 ,  H04L25/028 ,  H04L25/0286

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each pull up of the memory signal and a pre-emphasis on each pull down of the memory signal based on the delayed signal.

公开(公告)号：US09589626B1

公开(公告)日：2017-03-07

申请号：US14993271

申请日：2016-01-12

Applicant: Integrated Device Technology, Inc.

Inventor： HaiQi Liu ,  Yue Yu ,  Yumin Zhang ,  Yi Xie

IPC: G11C7/10 ,  G11C11/4074 ,  G11C11/4093 ,  G11C7/22

CPC classification number: G11C11/4074 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C11/4093

Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a data bus connected between a memory channel and a memory controller. The second circuit may be configured to condition the input signal relative to a reference voltage to generate a differential signal. The reference voltage may be isolated from the second circuit in response to a transition from a power down condition to a power on condition.

Abstract translation: 一种具有第一电路和第二电路的装置。 第一电路可以被配置为缓冲从连接在存储器通道和存储器控制器之间的数据总线作为单端信号接收的输入信号。 第二电路可以被配置为相对于参考电压调节输入信号以产生差分信号。 响应于从断电状态到电源接通状态的转变，参考电压可以与第二电路隔离。

公开(公告)号：US10565144B2

公开(公告)日：2020-02-18

申请号：US16059287

申请日：2018-08-09

Applicant: Integrated Device Technology, Inc.

Inventor： Alejandro F. Gonzalez ,  Craig DeSimone ,  Garret Davey ,  Yue Yu ,  Roland Knaack ,  Scott Herrington

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G11C7/22 ,  G11C11/4096 ,  G11C7/10

Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to operate with the memory devices having a first data width in a first mode and with the memory devices having a second data width in a second mode. The control circuit may be configured to implement two differential data strobe input/output circuits. The differential data strobe input/output circuits each may have driver and termination control inputs that are independently programmable. The differential data strobe input/output circuits may be configured to be connected in parallel when the control circuit is operating in the second mode.