公开(公告)号：US12289239B2

公开(公告)日：2025-04-29

申请号：US18154619

申请日：2023-01-13

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

公开(公告)号：US20240267334A1

公开(公告)日：2024-08-08

申请号：US18621516

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

CPC classification number: H04L47/125 ,  H04L47/62 ,  H04L47/624 ,  H04L47/6255 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

公开(公告)号：US12292842B2

公开(公告)日：2025-05-06

申请号：US17486579

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Anjali Jain ,  Reshma Lal ,  Edwin Verplanke ,  Priya Autee ,  Chih-Jen Chang ,  Abhirupa Layek ,  Nupur Jain

IPC: G06F13/38 ,  G06F13/16 ,  G06F13/28 ,  H04L45/02 ,  H04L45/64 ,  H04L67/289 ,  H04L69/321

Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

公开(公告)号：US20220286399A1

公开(公告)日：2022-09-08

申请号：US17637416

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Niall McDonnell ,  Gage Eads ,  Mrittika Ganguli ,  Chetan Hiremath ,  John Mangan ,  Stephen Palermo ,  Bruce Richardson ,  Edwin Verplanke ,  Praveen Mosur ,  Bradley Chaddick ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/625 ,  H04L47/62 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

公开(公告)号：US20230231809A1

公开(公告)日：2023-07-20

申请号：US18154619

申请日：2023-01-13

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

CPC classification number: H04L47/125 ,  H04L47/62 ,  H04L47/624 ,  H04L47/6255 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

公开(公告)号：US20220014459A1

公开(公告)日：2022-01-13

申请号：US17486579

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Anjali Jain ,  Reshma Lal ,  Edwin Verplanke ,  Priya Autee ,  Chih-Jen Chang ,  Abhirupa Layek ,  Nupur Jain

IPC: H04L12/751 ,  H04L12/715 ,  G06F13/28 ,  G06F13/16

Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

公开(公告)号：US12197601B2

公开(公告)日：2025-01-14

申请号：US17560193

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ren Wang ,  Sameh Gobriel ,  Somnath Paul ,  Yipeng Wang ,  Priya Autee ,  Abhirupa Layek ,  Shaman Narayana ,  Edwin Verplanke ,  Mrittika Ganguli ,  Jr-Shian Tsai ,  Anton Sorokin ,  Suvadeep Banerjee ,  Abhijit Davare ,  Desmond Kirkpatrick ,  Rajesh M. Sankaran ,  Jaykant B. Timbadiya ,  Sriram Kabisthalam Muthukumar ,  Narayan Ranganathan ,  Nalini Murari ,  Brinda Ganesh ,  Nilesh Jain

IPC: G06F15/78 ,  G06F9/50 ,  G06F21/62 ,  G06F21/72

Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

公开(公告)号：US11575607B2

公开(公告)日：2023-02-07

申请号：US17018809

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

公开(公告)号：US20210075730A1

公开(公告)日：2021-03-11

申请号：US17018809

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L12/803 ,  H04L12/863

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.