公开(公告)号：US12278229B2

公开(公告)日：2025-04-15

申请号：US18474275

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US20250116812A1

公开(公告)日：2025-04-10

申请号：US18983471

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes

IPC: G02B6/132 ,  G02B6/12 ,  G02B6/136

Abstract: Described herein are stacked photonic integrated circuit (PIC) assemblies that include multiple layers of waveguides. The waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. Layers of monocrystalline material are fabricated and repeatedly transferred onto the PIC structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. Layers of isolation materials are also deposited or layer transferred onto the PIC assembly.

公开(公告)号：US20250031362A1

公开(公告)日：2025-01-23

申请号：US18907358

申请日：2024-10-04

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert Dewey ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Jack Kavalieros

IPC: H10B12/00 ,  H01L21/683 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

公开(公告)号：US20250020873A1

公开(公告)日：2025-01-16

申请号：US18903219

申请日：2024-10-01

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Mauro J. Kobrinsky

IPC: G02B6/42 ,  G02B6/12 ,  G02B6/13 ,  H01L25/16 ,  H10B41/00

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. One or more additional electronic and/or photonic components may be provided in one or more of these IC structures after bonding. For example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded IC structures.

公开(公告)号：US12197007B2

公开(公告)日：2025-01-14

申请号：US17397352

申请日：2021-08-09

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes

IPC: G02B6/132 ,  G02B6/136 ,  G02B6/12

Abstract: Described herein are stacked photonic integrated circuit (PIC) assemblies that include multiple layers of waveguides. The waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. Layers of monocrystalline material are fabricated and repeatedly transferred onto the PIC structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. Layers of isolation materials are also deposited or layer transferred onto the PIC assembly.

公开(公告)号：US20240429162A1

公开(公告)日：2024-12-26

申请号：US18340072

申请日：2023-06-23

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Sagar Suthram ,  Anand S. Murthy ,  Wilfred Gomes

IPC: H01L23/528

Abstract: An example IC device includes a substrate comprising a plurality of areas and one or more scribe lines defining boundaries of individual areas of the plurality of areas. The plurality of areas includes a first area and a second area. The IC device further includes a scribe line between the first area and the second area, a first device layer over the first area of the substrate and a first metallization stack over the first device layer, a second device layer over the second area of the substrate and a second metallization stack over the second device layer, and a conductive line extending (e.g., being materially and electrically continuous) between the first metallization stack and the second metallization stack, where a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line.

公开(公告)号：US12068319B2

公开(公告)日：2024-08-20

申请号：US16141000

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani ,  Abhishek A. Sharma

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28194 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66537 ,  H01L29/6659

Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

公开(公告)号：US11950407B2

公开(公告)日：2024-04-02

申请号：US16828507

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Juan G. Alzate Vinasco ,  Travis W. Lajoie ,  Abhishek A. Sharma ,  Kimberly L Pierce ,  Elliot N. Tan ,  Yu-Jin Chen ,  Van H. Le ,  Pei-Hua Wang ,  Bernhard Sell

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/91 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/318 ,  H10B12/482 ,  H10B12/485

Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

公开(公告)号：US20240098965A1

公开(公告)日：2024-03-21

申请号：US17933589

申请日：2022-09-20

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Sagar Suthram

IPC: H01L27/108 ,  G11C5/06 ,  G11C5/10 ,  H01L23/48 ,  H01L25/065 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/11514

CPC classification number: H01L27/10876 ,  G11C5/063 ,  G11C5/10 ,  H01L23/481 ,  H01L25/0655 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/11514 ,  H01L27/10826 ,  H01L27/10879

Abstract: Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.

公开(公告)号：US20240088029A1

公开(公告)日：2024-03-14

申请号：US17930841

申请日：2022-09-09

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Sagar Suthram

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226

Abstract: Described herein are full wafer devices that include interconnect layers on a back side of the device. The backside interconnect layers couple together different dies of the full wafer device. The backside interconnect layers include an active layer that includes active devices, such as transistors. The active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.