公开(公告)号：US20250107156A1

公开(公告)日：2025-03-27

申请号：US18471710

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Robin Chao ,  Jaladhi Mehta ,  Tao Chu ,  Guowei Xu ,  Ting-Hsiang Hung ,  Feng Zhang ,  Yang Zhang ,  Chia-Ching Lin ,  Chung-Hsun Lin ,  Anand Murthy

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

公开(公告)号：US12255234B2

公开(公告)日：2025-03-18

申请号：US18409509

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20250089310A1

公开(公告)日：2025-03-13

申请号：US18466246

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Ting-Hsiang Hung ,  Yang Zhang ,  Robin Chao ,  Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Feng Zhang ,  Chia-Ching Lin ,  Anand Murthy

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

Abstract: Techniques are provided to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. A through-gate structure may extend in a third direction through an entire thickness of the gate structure and adjacent to the semiconductor region along the second direction. The through-gate structure may be a dielectric structure (e.g., a gate cut) or a conductive structure (e.g., a via). In either case, an airgap spacer exists between the through-gate structure and the gate structure.

公开(公告)号：US11996404B2

公开(公告)日：2024-05-28

申请号：US17540120

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0688 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1033 ,  H01L2221/68363

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11923421B2

公开(公告)日：2024-03-05

申请号：US17869622

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

CPC classification number: H01L29/165 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20240006413A1

公开(公告)日：2024-01-04

申请号：US17856869

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand Murthy

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L23/367 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L23/367 ,  H01L21/823814 ,  H01L21/823842

Abstract: Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.

公开(公告)号：US20230317558A1

公开(公告)日：2023-10-05

申请号：US17711848

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Wilfred Gomes ,  Anand Murthy ,  Tahir Ghani ,  Jack Kavalieros ,  Rajabali Koduri

IPC: H01L23/473 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L23/473 ,  H01L29/42392 ,  H01L29/0673

Abstract: Integrated circuit dies, systems, and techniques are described related to multiple transistor epitaxial layer source and drain transistor circuits operable at low temperatures. A system includes an integrated circuit die having a number of transistors each having a crystalline channel structure, a first layer epitaxial to the channel structure, and a second layer epitaxial to the first layer. The system further includes a cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

公开(公告)号：US11735630B2

公开(公告)日：2023-08-22

申请号：US16238858

申请日：2019-01-03

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Anupama Bowonder ,  Aaron Budrevich ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

公开(公告)号：US20230197614A1

公开(公告)日：2023-06-22

申请号：US17556422

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/8234

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/823475

Abstract: An integrated circuit structure includes a device layer including a plurality of transistors, a first interconnect feature vertically extending through the device layer, and an interconnect structure below the device layer. The interconnect structure below the device layer includes at least a second interconnect feature. In an example, the second interconnect feature is conjoined with the first interconnect feature. For example, the first and second interconnect features collectively form a continuous and monolithic body of conductive material.

公开(公告)号：US20230187507A1

公开(公告)日：2023-06-15

申请号：US17547980

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy ,  Aravind S. Killampalli

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: An integrated circuit includes a body of semiconductor material. A source or drain region includes semiconductor material in contact with the body, where the semiconductor material of the source or drain region includes an outer region having a dopant concentration that is greater than a remaining region of the source or drain region, the outer region defining multiple contact surfaces of the source or drain region and extending into the source or drain region to a depth of at least 1 nm. A contact comprising a metal is on the multiple contact surfaces of the source or drain region. The dopant concentration of the outer region is continuous along the entire interface between the contact and the outer region, according to an example.