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公开(公告)号：US20190317773A1
公开(公告)日：2019-10-17
申请号：US16388670
申请日：2019-04-18
Applicant: Intel Corporation
Inventor： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann
IPC: G06F9/4401 , G06F16/22 , G06F1/324 , G06F1/3234 , G06F9/44 , G06F1/26 , G06F9/22 , G06F9/445 , G06F11/36 , G06F1/3203 , G06F11/34 , G06F11/30 , G06F1/3296 , G06F1/28
Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
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公开(公告)号：US09494998B2
公开(公告)日：2016-11-15
申请号：US14109388
申请日：2013-12-17
Applicant: Intel Corporation
Inventor： Inder M. Sodhi , Barnes Cooper , Paul S. Diefenbaugh , Faraz A. Siddiqi , Michael Calyer , Andrew D. Henroid , Ruchika Singh
CPC classification number: G06F1/3243 , G06F1/3287 , G06F1/329 , G06F9/4893 , Y02D10/171 , Y02D10/24 , Y02D50/20
Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个核以独立地执行指令，至少一个图形引擎来独立地执行图形指令;以及功率控制器，其包括对准逻辑，以使至少一个工作负载在第一个核上被执行为 重新安排到不同的时间，以使得多个核心在活动时间窗口期间是活动的，并且在空闲时间窗口期间处于低功率状态。 描述和要求保护其他实施例。
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公开(公告)号：US20200334193A1
公开(公告)日：2020-10-22
申请号：US16916197
申请日：2020-06-30
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Guy G. Sotomayor , Andrew D. Henroid , Robert E. Gough , Tod F. Schiff
IPC: G06F15/00 , G06F1/20 , G06F1/3234 , G06F9/455 , G06F9/50
Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.
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公开(公告)号：US20180060078A1
公开(公告)日：2018-03-01
申请号：US15672254
申请日：2017-08-08
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V, Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
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公开(公告)号：US09874922B2
公开(公告)日：2018-01-23
申请号：US14623764
申请日：2015-02-17
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , James G. Hermerding, II
CPC classification number: G06F1/3206 , G06F1/3203 , G06F1/3287 , G06F9/50 , Y02B70/126 , Y02D10/171
Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US09842082B2
公开(公告)日：2017-12-12
申请号：US14633455
申请日：2015-02-27
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Guy G. Sotomayor , Andrew D. Henroid , Robert E. Gough , Tod F. Schiff
CPC classification number: G06F15/00 , G06F1/206 , G06F1/26 , G06F1/3243 , G06F9/45541 , G06F9/45558 , G06F9/5077 , G06F2009/4557 , Y02D10/152 , Y02D10/16
Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.
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公开(公告)号：US20170329377A1
公开(公告)日：2017-11-16
申请号：US15668771
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
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公开(公告)号：US10761579B2
公开(公告)日：2020-09-01
申请号：US15668771
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
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公开(公告)号：US09195285B2
公开(公告)日：2015-11-24
申请号：US13728335
申请日：2012-12-27
Applicant: Intel Corporation
Inventor： Eugene Gorbatov , Paul S. Diefenbaugh , Andrew D. Henroid , Guy M. Therien
CPC classification number: G06F1/206 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/16 , Y02D50/20
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for detecting active and semi-active workloads during execution on a platform processing device and enabling a duty cycle process to reduce thermal output and power consumption, and align unaligned activity. In various embodiments, the duty cycle processing may be enabled during an active workload when thermal output or power consumption is above a thermal threshold or power consumption threshold that is below an efficient operating point for the platform processing device. The duty cycle processing may also be enabled during semi-active workloads when the workload causes the platform processing device to be underutilized and unaligned. The duty cycle processing may comprise enabling a forced idle period for the platform processing device. Other embodiments are described and claimed.
Abstract translation: 各种实施例通常涉及用于在平台处理设备上的执行期间检测活动和半主动工作负载的装置，方法和其他技术，并且实现占空比过程以减少热输出和功率消耗，并且调整未对齐的活动。 在各种实施例中，当热输出或功率消耗高于低于用于平台处理设备的有效工作点的热阈值或功率消耗阈值时，可以在活动工作负载期间启用占空比处理。 当工作负载导致平台处理设备未充分利用和未对齐时，也可以在半主动工作负载期间启用占空比处理。 占空比处理可以包括为平台处理装置启用强制空闲周期。 描述和要求保护其他实施例。
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公开(公告)号：US11567896B2
公开(公告)日：2023-01-31
申请号：US16916197
申请日：2020-06-30
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Guy G. Sotomayor , Andrew D. Henroid , Robert E. Gough , Tod F. Schiff
Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.
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