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    Adaptively limiting a maximum operating frequency in a multicore processor
    2.
    发明授权
    Adaptively limiting a maximum operating frequency in a multicore processor 有权
    自适应地限制多核处理器中的最大工作频率

    公开(公告)号：US09377841B2

    公开(公告)日：2016-06-28

    申请号：US13889785

    申请日：2013-05-08

    Applicant: Intel Corporation

    Inventor： Ankush Varma ,  Ian Steiner ,  Avinash Ananthakrishnan ,  Krishnakanth Sistla ,  Chris Poirier ,  Matthew Bace ,  Eric Dehaemer

    IPC: G06F1/32

    CPC classification number: G06F1/324 ,  G06F1/3206 ,  Y02D10/126

    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元以控制处理器的功率消耗，其中功率控制单元包括控制逻辑以减少最大操作 如果在第一时间段内发生第一数量的强制执行状态转换或在第二时间段内发生第二数量的强制执行状态转换，则处理器的频率。 描述和要求保护其他实施例。

    ENERGY-AWARE POWER SHARING CONTROL
    4.
    发明申请
    ENERGY-AWARE POWER SHARING CONTROL 审中-公开

    公开(公告)号：US20190204900A1

    公开(公告)日：2019-07-04

    申请号：US15859265

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Sudheer Nair ,  James G. Hermerding, II ,  Avinash Ananthakrishnan

    IPC: G06F1/32

    CPC classification number: G06F1/3293 ,  G06F1/3206

    Abstract: Aspects of the embodiments are directed to systems, methods, and program products for rebalancing power in a multi-chip computing platform, which includes a core processor and a discrete peripheral processor. Embodiments include determining that the core processor and the discrete peripheral processor are in a limited usage state; altering a polling interval of the core processor and the discrete peripheral processor from a first polling time to a second polling time, the second polling time greater than the first polling time; and polling the core processor and the discrete peripheral processor after an expiration of the second polling time. Embodiments also include using thermal and/or energy consumption data to dynamically adjust polling times to permit the core processor and the discrete peripheral processor to remain in an idle or low power state for as long as possible.

    Sharing power between domains in a processor package using encoded power consumption information from a second domain to calculate an available power budget for a first domain
    7.
    发明授权
    Sharing power between domains in a processor package using encoded power consumption information from a second domain to calculate an available power budget for a first domain 有权
    使用来自第二域的编码功耗信息来共享处理器包中的域之间的电力，以计算第一域的可用功率预算

    公开(公告)号：US09423858B2

    公开(公告)日：2016-08-23

    申请号：US13628172

    申请日：2012-09-27

    Applicant: Intel Corporation

    Inventor： Xiuting C. Mann ,  Avinash Ananthakrishnan ,  Michael N. Derr ,  Craig Forbell

    IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20

    CPC classification number: G06F1/324 ,  G06F1/206 ,  G06F1/3206 ,  Y02D10/126 ,  Y02D10/16

    Abstract: In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to the first domain and having at least one non-core circuit, and a power control unit (PCU) coupled to the first and second domains. The PCU may include a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有至少一个核的第一域以执行指令的处理器，耦合到第一域并具有至少一个非核心电路的第二域和耦合到第一域的功率控制单元（PCU） 到第一和第二个域。 PCU可以包括功率共享逻辑以从第二域接收编码的功耗信息，并且至少部分地基于编码的功耗信息来计算第一域的可用功率预算。 描述和要求保护其他实施例。

    Energy-aware power sharing control
    10.
    发明授权
    Energy-aware power sharing control 有权

    公开(公告)号：US10606338B2

    公开(公告)日：2020-03-31

    申请号：US15859265

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Sudheer Nair ,  James G. Hermerding, II ,  Avinash Ananthakrishnan

    IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3293 ,  G06F1/3206 ,  G06F1/20 ,  G06F1/3287

    Abstract: Aspects of the embodiments are directed to systems, methods, and program products for rebalancing power in a multi-chip computing platform, which includes a core processor and a discrete peripheral processor. Embodiments include determining that the core processor and the discrete peripheral processor are in a limited usage state; altering a polling interval of the core processor and the discrete peripheral processor from a first polling time to a second polling time, the second polling time greater than the first polling time; and polling the core processor and the discrete peripheral processor after an expiration of the second polling time. Embodiments also include using thermal and/or energy consumption data to dynamically adjust polling times to permit the core processor and the discrete peripheral processor to remain in an idle or low power state for as long as possible.

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