公开(公告)号：US10795676B2

公开(公告)日：2020-10-06

申请号：US15721459

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed real and imaginary data elements; a second source register to store a second plurality of packed real and imaginary data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to select real and imaginary data elements in the first source register and second source register to multiply, the multiplier circuitry to multiply each selected imaginary data element in the first source register with a selected real data element in the second source register, and to multiply each selected real data element in the first source register with a selected imaginary data element in the second source register to generate a plurality of imaginary products, adder circuitry to add a first subset of the plurality of imaginary products to generate a first temporary result and to add a second subset of the plurality of imaginary products to generate a second temporary result; accumulation circuitry to combine the first temporary result with first data from a destination register to generate a first final result and to combine the second temporary result with second data from the destination register to generate a second final result and to store the first final result and second final result back in the destination register.

公开(公告)号：US11809867B2

公开(公告)日：2023-11-07

申请号：US17027230

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30 ,  G06F7/00

CPC classification number: G06F9/3001 ,  G06F7/00 ,  G06F9/30014 ,  G06F9/3016 ,  G06F9/30036

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed byte data elements; a second source register to store a second plurality of packed byte data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to concurrently multiply each of the packed byte data elements of the first plurality with a corresponding packed byte data element of the second plurality to generate a plurality of products; adder circuitry to add specified sets of the products to generate temporary results for each set of products; zero-extension or sign-extension circuitry to zero-extend or sign-extend the temporary result for each set to generate an extended temporary result for each set; accumulation circuitry to combine each of the extended temporary results with a selected packed data value stored in a third source register to generate a plurality of final results; and a destination register to store the plurality of final results as a plurality of packed data elements in specified data element positions.

公开(公告)号：US11573799B2

公开(公告)日：2023-02-07

申请号：US17226986

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Mark Charney ,  Robert Valentine ,  Jesus Corbal ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed doubleword data elements; a second source register to store a second plurality of packed doubleword data elements; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply a first doubleword data element from the first source register with a second doubleword data element from the second source register to generate a first quadword product and to concurrently multiply a third doubleword data element from the first source register with a fourth doubleword data element from the second source register to generate a second quadword product; and a destination register to store the first quadword product and the second quadword product as first and second packed quadword data elements.

公开(公告)号：US10802826B2

公开(公告)日：2020-10-13

申请号：US15721412

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed byte data elements; a second source register to store a second plurality of packed byte data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to concurrently multiply each of the packed byte data elements of the first plurality with a corresponding packed byte data element of the second plurality to generate a plurality of products; adder circuitry to add specified sets of the products to generate temporary results for each set of products; zero-extension or sign-extension circuitry to zero-extend or sign-extend the temporary result for each set to generate an extended temporary result for each set; accumulation circuitry to combine each of the extended temporary results with a selected packed data value stored in a third source register to generate a plurality of final results; and a destination register to store the plurality of final results as a plurality of packed data elements in specified data element positions.

公开(公告)号：US11256504B2

公开(公告)日：2022-02-22

申请号：US15721448

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers are described. A processor embodiment includes: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed real and imaginary data elements; a second source register to store a second plurality of packed real and imaginary data elements; and execution circuitry to execute the decoded instruction. The execution circuitry includes: multiplier circuitry to select real and imaginary data elements in the first source register and second source, multiply each selected imaginary data element in the first source register with a selected real data element in the second source register, and multiply each selected real data element in the first source register with a selected imaginary data element in the second source register to generate a plurality of imaginary products; adder circuitry to add a first subset of the plurality of imaginary products and subtract a second subset of the plurality of imaginary products to generate a first temporary result, and to add a third subset of the plurality of imaginary products and subtract a fourth subset of the plurality of imaginary products to generate a second temporary result; and accumulation circuitry to combine the first temporary result with first data from a destination register to generate a first final result, combine the second temporary result with second data from the destination register to generate a second final result, and store the first final result and second final result back in the destination register.

公开(公告)号：US10977039B2

公开(公告)日：2021-04-13

申请号：US16672203

申请日：2019-11-01

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Mark Charney ,  Robert Valentine ,  Jesus Corbal ,  Binwei Yang

IPC: G06F15/00 ,  G06F9/30

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed doubleword data elements; a second source register to store a second plurality of packed doubleword data elements; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply a first doubleword data element from the first source register with a second doubleword data element from the second source register to generate a first quadword product and to concurrently multiply a third doubleword data element from the first source register with a fourth doubleword data element from the second source register to generate a second quadword product; and a destination register to store the first quadword product and the second quadword product as first and second packed quadword data elements.

公开(公告)号：US11755323B2

公开(公告)日：2023-09-12

申请号：US17672504

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30105

Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers are described. A processor embodiment includes: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed real and imaginary data elements; a second source register to store a second plurality of packed real and imaginary data elements; and execution circuitry to execute the decoded instruction. The execution circuitry includes: multiplier circuitry to select real and imaginary data elements in the first source register and second source, multiply each selected imaginary data element in the first source register with a selected real data element in the second source register, and multiply each selected real data element in the first source register with a selected imaginary data element in the second source register to generate a plurality of imaginary products; adder circuitry to add a first subset of the plurality of imaginary products and subtract a second subset of the plurality of imaginary products to generate a first temporary result, and to add a third subset of the plurality of imaginary products and subtract a fourth subset of the plurality of imaginary products to generate a second temporary result; and accumulation circuitry to combine the first temporary result with first data from a destination register to generate a first final result, combine the second temporary result with second data from the destination register to generate a second final result, and store the first final result and second final result back in the destination register.

公开(公告)号：US11243765B2

公开(公告)日：2022-02-08

申请号：US15721145

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Mark Charney ,  Robert Valentine ,  Jesus Corbal ,  Binwei Yang

IPC: G06F9/302 ,  G06F9/30 ,  G06F7/544 ,  G06F17/14 ,  G06F7/48

Abstract: Apparatus and method to transform complex data including a processor that comprises: multiplier circuitry to multiply packed complex N-bit data elements with packed complex M-bit data elements to generate at least four real products; adder circuitry to subtract a first real product from a second real product to generate a first temporary result, subtract a third real product from a fourth real product to generate a second temporary result, add the first temporary result to a first packed N-bit data element to generate a first pre-scaled result, subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, add the second temporary result to a second packed N-bit data element to generate a third pre-scaled result, and subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; and scaling circuitry to scale the pre-scaled results.

公开(公告)号：US10552154B2

公开(公告)日：2020-02-04

申请号：US15721464

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30 ,  G06F7/48 ,  G06F7/52

Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers. A method comprises: multiplying selected imaginary and real data elements in a first and second source registers to generate a plurality of imaginary products; adding a first subset of the plurality of imaginary products to generate a first temporary result and adding a second subset of the plurality of imaginary products to generate a second temporary result; negating the first temporary result to generate a third temporary result and the second temporary result to generate a fourth temporary result; accumulating the third temporary result with first data to generate a first final result and accumulating the fourth temporary result with second data to generate a second final result; and storing the first final result and second final.

公开(公告)号：US10514924B2

公开(公告)日：2019-12-24

申请号：US15721261

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Mark Charney ,  Robert Valentine ,  Jesus Corbal ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed doubleword data elements; a second source register to store a second plurality of packed doubleword data elements; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply a first doubleword data element from the first source register with a second doubleword data element from the second source register to generate a first quadword product and to concurrently multiply a third doubleword data element from the first source register with a fourth doubleword data element from the second source register to generate a second quadword product; and a destination register to store the first quadword product and the second quadword product as first and second packed quadword data elements.