公开(公告)号：US11569161B2

公开(公告)日：2023-01-31

申请号：US16260623

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Chong Zhao ,  James McCall ,  Michael Gutzmann

IPC: H01L23/498 ,  H01L27/108

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, that comprises a bumpout region on a first surface of the package substrate, and a pin region on a second surface of the package substrate. In an embodiment, a data path from the bumpout region to the pin region is included in the electronic package. In an embodiment, a ground path brackets the data path from the bumpout region to the pin region.

公开(公告)号：US20190045632A1

公开(公告)日：2019-02-07

申请号：US16051573

申请日：2018-08-01

Applicant: Intel Corporation

Inventor： Xiang Li ,  Jun Liao ,  Yunhui CHU ,  George Vergis ,  Chong Zhao

IPC: H05K1/14 ,  H01R12/52 ,  H01R12/73 ,  H01R13/17

Abstract: Various aspects are related to a connector, e.g., for connecting two boards with one another. The connector may include a housing and a plurality of pins. The housing may include a first housing surface and a second housing surface opposite the first housing surface. Each pin of the plurality of pins may include a first portion protruding arcuately from the first housing surface and a second portion protruding arcuately from the second housing surface.

公开(公告)号：US11621237B2

公开(公告)日：2023-04-04

申请号：US16247312

申请日：2019-01-14

Applicant: Intel Corporation

Inventor： Jonathan W. Thibado ,  Jeffory L. Smalley ,  John C. Gulick ,  Phi Thanh ,  Mohanraj Prabhugoud ,  Chong Zhao

IPC: H05K1/02 ,  H01L23/66 ,  H01L23/498 ,  H01L23/34 ,  H01B7/04 ,  G02B6/42 ,  H01B3/30 ,  H01B7/08 ,  H01L25/10 ,  H05K1/18

Abstract: Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.