公开(公告)号：US20220336267A1

公开(公告)日：2022-10-20

申请号：US17850876

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Ramanan Chebiam ,  Brennen Mueller ,  Colin Carver ,  Jeffery Bielefeld ,  Nafees Kabir ,  Richard Vreeland ,  William Brezinski

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/00 ,  H04B1/40

Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

公开(公告)号：US11887887B2

公开(公告)日：2024-01-30

申请号：US17850876

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Ramanan Chebiam ,  Brennen Mueller ,  Colin Carver ,  Jeffery Bielefeld ,  Nafees Kabir ,  Richard Vreeland ,  William Brezinski

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535 ,  H01L23/00 ,  H04B1/40

CPC classification number: H01L21/76801 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/528 ,  H01L23/535 ,  H01L24/08 ,  H01L24/80 ,  H04B1/40 ,  H01L2224/08146 ,  H01L2224/80895

Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

公开(公告)号：US20220181251A1

公开(公告)日：2022-06-09

申请号：US17677858

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Richard Vreeland ,  Colin Carver ,  William Brezinski ,  Michael Christenson ,  Nafees Kabir

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

公开(公告)号：US20210098359A1

公开(公告)日：2021-04-01

申请号：US16584666

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Richard Vreeland ,  Colin Carver ,  William Brezinski ,  Michael Christenson ,  Nafees Kabir

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

公开(公告)号：US20240088701A1

公开(公告)日：2024-03-14

申请号：US17942392

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Naoki Matsumura ,  Colin Carver ,  Tod Schiff

IPC: H02J7/00 ,  G01R31/389

CPC classification number: H02J7/007182 ,  G01R31/389 ,  H02J7/00304 ,  H02J7/00308 ,  H02J7/0048 ,  H02J7/007194

Abstract: A constant voltage may be used during battery charging to reduce or avoid the formation of a dendrite, such as a stepped constant voltage. For each charging period, each level of the stepped constant voltage may be calculated to ensure a corresponding current level within each period remains below a safe current limit. A voltage transition between any two periods may occur in response to expiration of a predetermined time, or in response to a determination that the current level has fallen below a lower current limit. A current level during each period may be maintained such that the battery heat is maintained below a reference heat level, which may increase battery cycle life (e.g., battery capacity or maximum recharging cycles). The battery heat may be measured directly or indirectly, or may be estimated based on other measured or controlled values.

公开(公告)号：US11784123B2

公开(公告)日：2023-10-10

申请号：US17677858

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Richard Vreeland ,  Colin Carver ,  William Brezinski ,  Michael Christenson ,  Nafees Kabir

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3105

CPC classification number: H01L23/528 ,  H01L21/7684 ,  H01L21/76819 ,  H01L23/53238 ,  H01L23/53257 ,  H01L24/08 ,  H01L24/89 ,  H01L21/31053 ,  H01L21/3212 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

公开(公告)号：US11289421B2

公开(公告)日：2022-03-29

申请号：US16584666

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Richard Vreeland ,  Colin Carver ,  William Brezinski ,  Michael Christenson ,  Nafees Kabir

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3105

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

公开(公告)号：US20210098360A1

公开(公告)日：2021-04-01

申请号：US16586279

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Ramanan Chebiam ,  Brennen Mueller ,  Colin Carver ,  Jeffery Bielefeld ,  Nafees Kabir ,  Richard Vreeland ,  William Brezinski

IPC: H01L23/528 ,  H01L23/535 ,  H01L23/00 ,  H04B1/40

Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.