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    SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY
    4.
    发明申请
    SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY 审中-公开
    堆叠存储器的系统，方法和装置

    公开(公告)号：US20150161005A1

    公开(公告)日：2015-06-11

    申请号：US14622776

    申请日：2015-02-13

    Applicant: Intel Corporation

    Inventor： Bryan K. Casper ,  Stephen R. Mooney ,  David Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

    IPC: G06F11/10 ,  H03M13/15 ,  G11C5/02

    CPC classification number: G06F11/1076 ,  G11C5/02 ,  G11C29/12 ,  H01L2224/16145 ,  H03M13/15 ,  H03M13/152

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

    Abstract translation: 本发明的实施例一般涉及用于混合存储器的系统，方法和装置。 在一个实施例中，混合存储器可以包括封装衬底。 混合存储器还可以包括附接到封装衬底的第一侧的混合存储器缓冲芯片。 高速输入/输出（HSIO）逻辑支持与处理器的HSIO接口。 混合存储器还包括在HSIO接口上支持分组处理协议的分组处理逻辑。 此外，混合存储器还具有垂直堆叠在混合存储器缓冲器上的一个或多个存储器片。

    Systems, methods, and apparatuses for stacked memory
    5.
    发明授权
    Systems, methods, and apparatuses for stacked memory 有权

    公开(公告)号：US11003534B2

    公开(公告)日：2021-05-11

    申请号：US16844925

    申请日：2020-04-09

    Applicant: Intel Corporation

    Inventor： Bryan K. Casper ,  Stephen R. Mooney ,  David Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

    IPC: G06F11/10 ,  H03M13/15 ,  G11C29/12 ,  G11C5/02

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

    Systems, methods, and apparatuses for stacked memory
    7.
    发明授权
    Systems, methods, and apparatuses for stacked memory 有权

    公开(公告)号：US10956268B2

    公开(公告)日：2021-03-23

    申请号：US16529716

    申请日：2019-08-01

    Applicant: Intel Corporation

    Inventor： Bryan K. Casper ,  Stephen R. Mooney ,  David Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

    IPC: G06F11/10 ,  H03M13/15 ,  G11C29/12 ,  G11C5/02

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

    SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY
    8.
    发明申请
    SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY 审中-公开

    公开(公告)号：US20200233746A1

    公开(公告)日：2020-07-23

    申请号：US16844925

    申请日：2020-04-09

    Applicant: Intel Corporation

    Inventor： Bryan K. CASPER ,  Stephen R. Mooney ,  David Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

    IPC: G06F11/10 ,  H03M13/15 ,  G11C29/12 ,  G11C5/02

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

    SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY
    9.
    发明申请
    SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY 审中-公开

    公开(公告)号：US20190354437A1

    公开(公告)日：2019-11-21

    申请号：US16529716

    申请日：2019-08-01

    Applicant: Intel Corporation

    Inventor： Bryan K. CASPER ,  Stephen R. Mooney ,  David Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

    IPC: G06F11/10 ,  H03M13/15 ,  G11C5/02 ,  G11C29/12

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

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