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    Programmable logic device with fine-grained disaggregation
    2.
    发明授权
    Programmable logic device with fine-grained disaggregation 有权

    公开(公告)号：US12206410B2

    公开(公告)日：2025-01-21

    申请号：US18169988

    申请日：2023-02-16

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

    IPC: H03K19/1776 ,  H01L23/367 ,  H01L25/18

    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

    Techniques For Clock Signal Transmission In Integrated Circuits And Interposers
    5.
    发明申请
    Techniques For Clock Signal Transmission In Integrated Circuits And Interposers 有权

    公开(公告)号：US20230049681A1

    公开(公告)日：2023-02-16

    申请号：US17973428

    申请日：2022-10-25

    Applicant: Intel Corporation

    Inventor： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

    IPC: G06F1/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

    Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.

    PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION
    8.
    发明申请
    PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION 审中-公开

    公开(公告)号：US20200186149A1

    公开(公告)日：2020-06-11

    申请号：US16788760

    申请日：2020-02-12

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

    IPC: H03K19/1776 ,  H01L25/18 ,  H01L23/367

    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

    Dual in-line memory module (DIMM) programmable accelerator card
    9.
    发明授权
    Dual in-line memory module (DIMM) programmable accelerator card 有权

    公开(公告)号：US10649927B2

    公开(公告)日：2020-05-12

    申请号：US16211868

    申请日：2018-12-06

    Applicant: Intel Corporation

    Inventor： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

    IPC: G06F13/38 ,  G06F13/16 ,  G06F13/12 ,  G06F13/42

    Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.

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