公开(公告)号：US20220245752A1

公开(公告)日：2022-08-04

申请号：US17685445

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/38

Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.

公开(公告)号：US20210266836A1

公开(公告)日：2021-08-26

申请号：US17307816

申请日：2021-05-04

Applicant: Intel Corporation

Inventor： Eric C. Samson ,  Murali Ramadoss ,  Marc Beuchat

IPC: H04W52/02 ,  H04W52/18 ,  G06T1/20 ,  G06F1/324 ,  G06F1/3234

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200042417A1

公开(公告)日：2020-02-06

申请号：US16526069

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Balaji Vembu ,  Josh B. Mastronarde ,  Altug Koker ,  Eric C. Samson ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F11/30 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3296 ,  G05F1/10 ,  G05F1/571 ,  G06F11/32 ,  G06F11/34

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

公开(公告)号：US10178619B1

公开(公告)日：2019-01-08

申请号：US15720906

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Eric C. Samson ,  Murali Ramadoss ,  Marc Beuchat

IPC: H04W52/02 ,  H04B7/06 ,  H04M1/73 ,  H04W52/18 ,  G06T1/20

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US20160026229A1

公开(公告)日：2016-01-28

申请号：US14875930

申请日：2015-10-06

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Jeremy J. Shrall ,  Eric C. Samson ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3243 ,  G06F13/14 ,  Y02D10/126

Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

公开(公告)号：US20150332428A1

公开(公告)日：2015-11-19

申请号：US14810963

申请日：2015-07-28

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Eric C. Samson ,  Robert B. Taylor

IPC: G06T1/20 ,  G09G5/395 ,  G09G5/00 ,  G06T1/60 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06T1/00 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G5/395 ,  G09G2330/021 ,  G09G2360/08 ,  G09G2360/122 ,  G09G2360/18

Abstract: In accordance with some embodiments, partial rendering of non-changing or slowly changing frame tiles allows the graphics processing unit to spend less time processing non-changing or slowly changing portions of each frame, saving power and creating more room for performance in some embodiments.

Abstract translation: 根据一些实施例，不改变或缓慢变化的帧瓦片的部分渲染允许图形处理单元花费更少的时间处理每个帧的不变或缓慢变化的部分，从而在一些实施例中节省功率并创造更多的性能空间。

公开(公告)号：US20200319806A1

公开(公告)日：2020-10-08

申请号：US16715747

申请日：2019-12-16

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Alon Naveh ,  Doron Rajwan ,  Ryan D. Wells ,  Eric C. Samson

IPC: G06F3/06 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

公开(公告)号：US10430310B2

公开(公告)日：2019-10-01

申请号：US15477031

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Balaji Vembu ,  Josh B. Mastronarde ,  Altug Koker ,  Eric C. Samson ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F1/00 ,  G06F11/30 ,  G06F1/3206 ,  G06F1/3296 ,  G05F1/10 ,  G05F1/571 ,  G06F11/32 ,  G06F11/34 ,  G06F1/324

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190215769A1

公开(公告)日：2019-07-11

申请号：US16243029

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Eric C. Samson ,  Murali Ramadoss ,  Marc Beuchat

IPC: H04W52/02 ,  G06T1/20 ,  H04W52/18

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US10242652B2

公开(公告)日：2019-03-26

申请号：US14959455

申请日：2015-12-04

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Eric C. Samson

IPC: G09G5/36 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/26 ,  G06F1/3234 ,  G06F1/329

Abstract: Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.