公开(公告)号：US11569161B2

公开(公告)日：2023-01-31

申请号：US16260623

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Chong Zhao ,  James McCall ,  Michael Gutzmann

IPC: H01L23/498 ,  H01L27/108

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, that comprises a bumpout region on a first surface of the package substrate, and a pin region on a second surface of the package substrate. In an embodiment, a data path from the bumpout region to the pin region is included in the electronic package. In an embodiment, a ground path brackets the data path from the bumpout region to the pin region.

公开(公告)号：US20210408704A1

公开(公告)日：2021-12-30

申请号：US17470552

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Xiang Li ,  George Vergis ,  James McCall ,  Qin Li

IPC: H01R12/71 ,  H01R12/55 ,  H05K1/18 ,  H01R13/24

Abstract: Systems, apparatuses and methods may provide for a memory module that includes a dynamic random access memory (DRAM), a first plurality of contact pads positioned along a first side of the DRAM, a first plurality of L-shaped contacts, wherein each of the first plurality of L-shaped contacts is soldered to one of the first plurality of contact pads, a second plurality of contact pads positioned along a second side of the DRAM, and a second plurality of L-shaped contacts, wherein each of the second plurality of L-shaped contacts is soldered to one of the second plurality of contact pads.

公开(公告)号：US11657862B2

公开(公告)日：2023-05-23

申请号：US16361837

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Rogelio Alfonso Moreyra Gonzalez ,  Jose Angel Ramos Martinez ,  James McCall

IPC: G11C5/06 ,  G11C7/22 ,  H05K1/18 ,  H05K1/02 ,  G11C5/04

CPC classification number: G11C7/222 ,  H05K1/0298 ,  H05K1/181 ,  G11C5/04 ,  H05K2201/09227 ,  H05K2201/09327 ,  H05K2201/10159

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to facilitating increased clock speeds on a substrate by lowering the impedance of traces that provide clock signals to components such as DRAM. For example, embodiments may include a substrate with a first layer and a second layer parallel to the first layer with a first trace coupled with the first layer in a routing configuration and a second trace coupled with the second layer in the routing configuration, where the routing configuration of the first trace and the second trace substantially overlap each other with respect to an axis perpendicular to the first layer and the second layer, and where the first trace and the second trace are electrically coupled by a first and a second electrical coupling perpendicular to the first layer and the second layer.

公开(公告)号：US10729002B2

公开(公告)日：2020-07-28

申请号：US16516174

申请日：2019-07-18

Applicant: Intel Corporation

Inventor： Jun Liao ,  Xiang Li ,  Yunhui Chu ,  Jong-Ru Guo ,  James McCall

IPC: H05K1/02 ,  H05K1/11 ,  H03F3/16 ,  H03F3/68 ,  H05K1/18 ,  H03F3/45 ,  G09G5/00 ,  H05K1/14

Abstract: Techniques and mechanisms for mitigating signal deterioration in communications between two circuit boards. In an embodiment, a packaged device accommodates coupling to a first circuit board which, in turn, accommodates connection to a second circuit board. In one such embodiment, an amplifier circuit of the packaged device includes an amplifier circuit which comprises a variable resistor and an active circuit element coupled thereto. The device receives via one of the circuit boards a control signal and a voltage which configure the amplifier circuit to provide an impedance matching for communication between the circuit boards. In another embodiment, the device comprises multiple common gate amplifiers which are variously configurable each to provide a respective impedance matching for communications between a motherboard and a dual in-line memory module.