公开(公告)号：US20230420346A1

公开(公告)日：2023-12-28

申请号：US17846303

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Yi Yang ,  Suddhasattwa Nad ,  Ali Lehaf ,  Jason Steill

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49894 ,  H01L21/4857 ,  H01L21/4853

Abstract: Various embodiments disclosed relate to a semiconductor assembly interconnect structure. The present disclosure includes an interconnect structure that case include a substrate, a metallic layer thereon, an adhesion promoter film formed over the metallic layer and forming a flat region over a flat portion of the metallic layer, a solder resist layer formed over the adhesion promoter film, an opening in the solder resist layer and the adhesion promoter film in the flat region of the adhesion promotion film, the opening connecting to the flat portion of the metallic layer, and a stacked electrical connector formed on the metallic layer within the opening. Methods of making an interconnect structure can include patterning a metallic layer on a substrate, depositing an adhesion promoter layer on the metallic layer opposite the substrate, patterning the adhesion promoter layer to expose selected portions of the metallic layer, and depositing a surface finish layer on the exposed selected portions of the metallic layer.

公开(公告)号：US20240006299A1

公开(公告)日：2024-01-04

申请号：US17855568

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jason Steill ,  Yi Yang ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Marcel Arlan Wall ,  Gang Duan ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49833 ,  H01L23/49822 ,  H01L21/4857

Abstract: Disclosed herein are microelectronics package architectures utilizing SiNx based surface finishes and methods of manufacturing the same. The microelectronics packages may include a core material, a first plurality of pads, and a silicon nitride layer. The first plurality of pads are attached to the core material. The silicon nitride layer is attached to the core material. The silicon nitride material defines respective openings to expose at least a portion of each of the first plurality of pads.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/485 ,  H01L23/49827

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20220102259A1

公开(公告)日：2022-03-31

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20250006616A1

公开(公告)日：2025-01-02

申请号：US18216521

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Kristof Darmawikarta ,  Jason Steill ,  Srinivas Pietambaram ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: IC die package with hybrid metallization surfaces. Routing metallization features have lower surface roughness for reduced high-frequency signal transmission losses while IC die attach metallization features have higher surface roughness for greater adhesion. Routing and die attach features may be formed within a same package metallization level, for example with a plating process. An insulator material may be formed over the surface of the metallization features, for example with a dry film lamination process. Optionally, an interface material may be deposited upon at least the routing features to enhance adhesion of the insulator material to metallization surfaces of low roughness. An opening in the insulator material may be formed to expose a surface of a die attach feature. The exposed surface may be selectively roughened, and an IC die attached to the roughened surface.

公开(公告)号：US20240222035A1

公开(公告)日：2024-07-04

申请号：US18090305

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Kristof Darmawikarta ,  Benjamin Duong ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Jason Steill ,  Thomas Sounart ,  Darko Grujicic

IPC: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/165 ,  H01L23/3675

Abstract: Apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. The multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.

公开(公告)号：US20240006291A1

公开(公告)日：2024-01-04

申请号：US17855961

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jeremy D. Ecton ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Steill ,  Yi Yang ,  Marcel Arlan Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49894 ,  H01L23/49816

Abstract: A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.

公开(公告)号：US20230420353A1

公开(公告)日：2023-12-28

申请号：US17848053

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Yi Yang ,  Jason Steill ,  Jieying Kong

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49894 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4864 ,  H01L2924/35121 ,  H01L24/16

Abstract: An electronic device package comprises a substrate with a first side and a second side opposite the first side; a first conductive feature on the first side and having a first surface; a first dielectric material in contact with the first surface, wherein the first dielectric material has a first composition comprising silicon and nitrogen; a second conductive feature on the second side of the substrate and having a second surface; and a second dielectric material in contact with the second surface, wherein the second dielectric material has a second composition different than the first composition, and wherein a surface roughness of the second surface is greater than a surface roughness of the first surface.

公开(公告)号：US20230420298A1

公开(公告)日：2023-12-28

申请号：US17851999

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Cemil Serdar Geyik ,  Jiwei Sun ,  Jason Steill

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L2225/06541 ,  H01L2224/13025 ,  H01L2224/0401 ,  H01L25/0655

Abstract: An electronic device comprises a substrate layer comprising a first side and an opposing second side, a through hole passing through the substrate layer between the first side and the second side, a first electrical pathway passing from a first position on the first side of the substrate layer, through a first portion of the through hole, to a first corresponding position on the second side of the substrate layer, a second electrical pathway passing from a second position on the first side of the substrate layer, through a second portion of the through hole, to a corresponding second position on the second side of the substrate layer, and an insulation layer between the first electrical pathway and the second electrical pathway within the through hole, wherein the insulation layer electrically isolates the first electrical pathway from the second electrical pathway.