公开(公告)号：US20210248085A1

公开(公告)日：2021-08-12

申请号：US16973998

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Zhaojuan Bian ,  Kebing Wang

IPC: G06F12/1045 ,  G06F12/06 ,  G06F12/0882 ,  G06F12/02 ,  G06F12/0871

Abstract: Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.

公开(公告)号：US11615034B2

公开(公告)日：2023-03-28

申请号：US16973998

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Zhaojuan Bian ,  Kebing Wang

IPC: G06F12/10 ,  G06F12/1045 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0871 ,  G06F12/0882

Abstract: Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.

公开(公告)号：US20230281134A1

公开(公告)日：2023-09-07

申请号：US18187092

申请日：2023-03-21

Applicant: Intel Corporation

Inventor： Zhaojuan Bian ,  Kebing Wang

IPC: G06F12/1045 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882

CPC classification number: G06F12/1045 ,  G06F12/0653 ,  G06F12/0246 ,  G06F12/0871 ,  G06F12/0882 ,  G06F2212/7201

Abstract: Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.

公开(公告)号：US09836400B2

公开(公告)日：2017-12-05

申请号：US14126921

申请日：2013-10-31

Applicant: Intel Corporation

Inventor： Kebing Wang ,  Zhaojuan Bian ,  Wei Zhou ,  Zhihong Wang

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0831 ,  G06F12/0811

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0833 ,  G06F2212/283 ,  G06F2212/621 ,  Y02D10/13

Abstract: In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.