公开(公告)号：US20240012497A1

公开(公告)日：2024-01-11

申请号：US17860388

申请日：2022-07-08

Applicant: Intel Corporation

Inventor： Isaac Abraham ,  Michael W. Altmann ,  Jonathan Kolet Gamble ,  Rodolfo Kiyama Armendariz

IPC: G06F3/038 ,  G06F3/044 ,  G06F3/041 ,  H03H11/44 ,  H03H11/12

CPC classification number: G06F3/0383 ,  G06F3/044 ,  G06F3/0416 ,  H03H11/44 ,  H03H11/1278

Abstract: Data transfer rates input to and output from electronic devices are a function of I/O pad circuit structure. The load capacitance of an I/O pad may reduce the bandwidth of an I/O circuit. A reduced pad capacitance circuit may be used to reduce or eliminate the positive and physical pad capacitance associated with a capacitive pad. This negative capacitance reduces or minimizes poor signal quality arising from large pad capacitance. This improved signal may be fed into a comparator, where the signal may be improved further using an equalizer. The use of negative capacitance circuit will increase the transmit and receive signaling quality of I/O interfaces.

公开(公告)号：US20180183633A1

公开(公告)日：2018-06-28

申请号：US15391593

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Yick Yaw Darren Ho ,  Michael W. Altmann

IPC: H04L25/03

CPC classification number: H04L7/033

Abstract: Some embodiments include apparatus and methods using clock generation circuitry to generate a first clock signal and a second clock signal based on an input clock signal, the first and second clock signals having different phases, sampler circuitry to sample an input signal based on timing of the first and second clock signals and provide data information and error information associated with sampling of the input signal, a clock and data recovery unit to generate first control information based on the data information and the error information, and a phase error detection unit to generate second control information based on the data information and the error information, the clock generation circuitry to control timing of the input clock signal based on the first control information and to control timing of the first and second clock signals based on the second control information.

公开(公告)号：US20210405090A1

公开(公告)日：2021-12-30

申请号：US16912612

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Liwei Zhao ,  Andrew Martwick ,  Michael W. Altmann ,  Michael Mirmak ,  Kamel Ahmad ,  Andrew Holland

IPC: G01R13/02

Abstract: A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope

公开(公告)号：US11614468B2

公开(公告)日：2023-03-28

申请号：US16912612

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Liwei Zhao ,  Andrew Martwick ,  Michael W. Altmann ,  Michael Mirmak ,  Kamel Ahmad ,  Andrew Holland

IPC: G01R13/02

Abstract: A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope.

公开(公告)号：US10944411B1

公开(公告)日：2021-03-09

申请号：US16728601

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Mark Elzinga ,  Youngmin Park ,  Michael Bichan ,  Michael W. Altmann ,  Noam Familia ,  Vadim Levin ,  Dror Lazar

IPC: H03L7/10 ,  H03M3/00 ,  H03L7/099 ,  H03L7/18 ,  H03L7/187

Abstract: Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.