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公开(公告)号：US20190204886A1
公开(公告)日：2019-07-04
申请号：US16299019
申请日：2019-03-11
Applicant: Intel Corporation
Inventor： Michael Zelikson , Vjekoslav Svilan , Norbert Unger , Shai Rotem
IPC: G06F1/26 , G06F1/3287 , G06F1/3234 , H03K17/687
CPC classification number: G06F1/26 , G06F1/3243 , G06F1/3287 , H03K17/687 , Y02D10/152 , Y02D10/171
Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.
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公开(公告)号：US10203742B2
公开(公告)日：2019-02-12
申请号：US15290619
申请日：2016-10-11
Applicant: Intel Corporation
Inventor： Gregory Sizikov , Michael Zelikson , Efraim Rotem , Eyal Fayneh
Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
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公开(公告)号：US20150169025A1
公开(公告)日：2015-06-18
申请号：US14634481
申请日：2015-02-27
Applicant: Intel Corporation
Inventor： Gregory Sizikov , Michael Zelikson , Efraim Rotem , Eyal Fayneh
Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
Abstract translation: 这里描述的集成电路包括：具有一个或多个桥式驱动器的开关电压调节器（SVR），以向多个电源域提供稳定的电源; 以及功率控制单元（PCU），其可操作以根据所述多个功率域的状态来调整所述SVR的开关频率，其中所述一个或多个桥接驱动器的驱动强度或有源相位计数也由所述SVR的逻辑单元 当SVR的开关频率被调整时。
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4.发明授权公开(公告)号：US11429173B2
公开(公告)日：2022-08-30
申请号：US16230440
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Chee Lim Nge , Amit Jain , Anant Deval , Nimrod Angel , Fabrice Paillet , Michael Zelikson , Sergio Carlo Rodriguez
IPC: G06F1/26 , G06F1/32 , G06F1/3206 , H02M3/158 , H02M1/08 , G06F1/20 , G06F1/3296 , H02M1/32 , G06F1/324 , H02M1/00 , H02M3/156
Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.
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公开(公告)号：US10536139B2
公开(公告)日：2020-01-14
申请号：US15958768
申请日：2018-04-20
Applicant: Intel Corporation
Inventor： Shai Rotem , Norbert Unger , Michael Zelikson
IPC: H03K17/00 , H03K17/687
Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.
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Patent Agency Ranking
公开(公告)号：US10156859B2
公开(公告)日：2018-12-18
申请号：US14129860
申请日：2013-09-26
Applicant: Intel Corporation
Inventor： Kosta Luria , Alexander Lyakhov , Joseph Shor , Michael Zelikson
Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.
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公开(公告)号：US11429172B2
公开(公告)日：2022-08-30
申请号：US16735563
申请日：2020-01-06
Applicant: Intel Corporation
Inventor： Alexander Uan-Zo-Li , Eugene Gorbatov , Harish Krishnamurthy , Alexander Lyakhov , Patrick Leung , Stephen Gunther , Arik Gihon , Khondker Ahmed , Philip Lehwalder , Sameer Shekhar , Vishram Pandit , Nimrod Angel , Michael Zelikson
Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.
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公开(公告)号：US11342852B2
公开(公告)日：2022-05-24
申请号：US15631996
申请日：2017-06-23
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit K. Jain , Alexander Waizman , Michael Zelikson , Chin Lee Kuan
Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.
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公开(公告)号：US20170031419A1
公开(公告)日：2017-02-02
申请号：US15290619
申请日：2016-10-11
Applicant: Intel Corporation
Inventor： Gregory Sizikov , Michael Zelikson , Efraim Rotem , Eyal Fayneh
Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
Abstract translation: 这里描述的集成电路包括：具有一个或多个桥式驱动器的开关电压调节器（SVR），以向多个电源域提供稳定的电源; 以及功率控制单元（PCU），其可操作以根据所述多个功率域的状态来调整所述SVR的开关频率，其中所述一个或多个桥接驱动器的驱动强度或有源相位计数也由所述SVR的逻辑单元 当SVR的开关频率被调整时。
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公开(公告)号：US09477291B2
公开(公告)日：2016-10-25
申请号：US14634481
申请日：2015-02-27
Applicant: Intel Corporation
Inventor： Gregory Sizikov , Michael Zelikson , Efraim Rotem , Eyal Fayneh
Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
Abstract translation: 这里描述的集成电路包括：具有一个或多个桥式驱动器的开关电压调节器（SVR），以向多个电源域提供稳定的电源; 以及功率控制单元（PCU），其可操作以根据所述多个功率域的状态来调整所述SVR的开关频率，其中所述一个或多个桥接驱动器的驱动强度或有源相位计数也由所述SVR的逻辑单元 当SVR的开关频率被调整时。
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