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    RRAM devices with reduced forming voltage
    2.
    发明授权
    RRAM devices with reduced forming voltage 有权

    公开(公告)号：US11342499B2

    公开(公告)日：2022-05-24

    申请号：US16630845

    申请日：2017-09-18

    Applicant: Intel Corporation

    Inventor： Timothy E. Glassman ,  Dragos Seghete ,  Nathan Strutt ,  Namrata S. Asuri ,  Oleg Golonzka

    IPC: H01L29/02 ,  H01L45/00 ,  G11C13/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/24

    Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.

    Resistive random access memory device and methods of fabrication
    3.
    发明授权
    Resistive random access memory device and methods of fabrication 有权

    公开(公告)号：US11502254B2

    公开(公告)日：2022-11-15

    申请号：US16147199

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Nathan Strutt ,  Albert Chen ,  Oleg Golonzka

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A memory device structure includes a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, where the switching layer is to transition between first and second resistive states at a voltage threshold. The memory device further includes an oxygen exchange layer between the switching layer and the second electrode, where the oxygen exchange layer includes a metal and a sidewall oxide in contact with a sidewall of the oxygen exchange layer. The sidewall oxide includes the metal of the oxygen exchange layer and oxygen, and has a lateral thickness that exceed a thickness of the switching layer.

    RESISTIVE RANDOM-ACCESS MEMORY DEVICES AND METHODS OF FABRICATION
    4.
    发明申请
    RESISTIVE RANDOM-ACCESS MEMORY DEVICES AND METHODS OF FABRICATION 审中-公开

    公开(公告)号：US20200343445A1

    公开(公告)日：2020-10-29

    申请号：US16396465

    申请日：2019-04-26

    Applicant: Intel Corporation

    Inventor： Nathan Strutt ,  Albert Chen ,  Pedro Quintero ,  Oleg Golonzka

    IPC: H01L45/00 ,  G11C13/00

    Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

    Resistive random-access memory devices and methods of fabrication
    5.
    发明授权
    Resistive random-access memory devices and methods of fabrication 有权

    公开(公告)号：US11621395B2

    公开(公告)日：2023-04-04

    申请号：US16396465

    申请日：2019-04-26

    Applicant: Intel Corporation

    Inventor： Nathan Strutt ,  Albert Chen ,  Pedro Quintero ,  Oleg Golonzka

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

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