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    Adaptive virtual function drivers for electronic devices
    1.
    发明授权
    Adaptive virtual function drivers for electronic devices 有权

    公开(公告)号：US11989573B2

    公开(公告)日：2024-05-21

    申请号：US18204643

    申请日：2023-06-01

    Applicant: INTEL CORPORATION

    Inventor： Anjali Singhai Jain ,  Mitu Aggarwal ,  Parthasarathy Sarangam ,  Donald Wood ,  Jesse Brandeburg ,  Mitchell A. Williams

    IPC: G06F9/455 ,  G06F8/61 ,  G06F13/10

    CPC classification number: G06F9/45537 ,  G06F8/63 ,  G06F13/102 ,  G06F9/45558

    Abstract: Techniques for providing adaptive virtual function (VF) drivers capable of operating with physical devices having a plurality of different hardware configurations are described. In one embodiment, for example, an apparatus may include logic to implement a virtual machine (VM), the logic to initialize an adaptive virtual function (VF) driver to facilitate communication between the VM and a physical device to be virtualized, establish communication between the adaptive VF driver and a physical function (PF) driver of the hypervisor for the physical device, activate a standard feature set for the adaptive VF driver to execute on a PF of the physical device, and negotiate activation of an advanced feature set for the adaptive VF driver to execute on the PF, the adaptive VF driver to provide the advanced feature set to the PF, the PF activate each feature of the advanced feature set supported by the PF.

    Reorder resilient transport
    4.
    发明授权
    Reorder resilient transport 有权

    公开(公告)号：US11502952B2

    公开(公告)日：2022-11-15

    申请号：US15969017

    申请日：2018-05-02

    Applicant: Intel Corporation

    Inventor： Anil Vasudevan ,  Parthasarathy Sarangam ,  Eric Mann ,  Daniel Cohn

    IPC: H04L1/00 ,  H04L45/74 ,  H04L47/11 ,  H04L47/52 ,  H04L47/50 ,  H04L45/00

    Abstract: Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.

    ADAPTIVE INTERRUPT MODERATION
    6.
    发明申请
    ADAPTIVE INTERRUPT MODERATION 审中-公开
    自适应中断调制

    公开(公告)号：US20150186307A1

    公开(公告)日：2015-07-02

    申请号：US14642967

    申请日：2015-03-10

    Applicant: Intel Corporation

    Inventor： Yadong Li ,  Linden Cornett ,  Manasi Deval ,  Anil Vasudevan ,  Parthasarathy Sarangam

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  H04L69/165

    Abstract: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.

    Abstract translation: 通常，本公开涉及自适应中断调节。 方法可以包括：至少部分地基于与每个连接相关联的连接标识符，由主机设备确定主机设备与一个或多个链路伙伴之间的连接数; 由所述主机设备至少部分地基于多个连接来确定新的中断率; 通过所述主机设备更新具有与所述新中断速率相关的值的中断调节定时器; 并配置中断调节定时器以允许以新的中断速率发生中断。

    Flexible scheme for adding rules to a NIC pipeline
    7.
    发明授权
    Flexible scheme for adding rules to a NIC pipeline 有权

    公开(公告)号：US12218840B2

    公开(公告)日：2025-02-04

    申请号：US16902371

    申请日：2020-06-16

    Applicant: Intel Corporation

    Inventor： Manasi Deval ,  Elazar Cohen ,  Shaul Yifrach ,  Parthasarathy Sarangam

    IPC: H04L45/7453 ,  H04L45/00 ,  H04L45/745 ,  H04L69/22

    Abstract: Flexible schemes for adding rules to a NIC pipeline and associated apparatus. Multiple match-action tables are implemented in host memory of a platform defining actions to be taken for matching packet flows. A packet processing pipeline and an exact match (EM) cache is implemented on a network interface, such as a NIC, installed in the platform. A portion of the match-action entries in the host memory match-action tables are cached in the EM cache. Received packets are processed to generate a key that is used as a lookup for the EM cache. If a match is found, the action is taken. For a miss, the key is forwarded to the host software and the match-action tables are searched. For a match, the action is taken, and the entry is added to the EM cache. If no match is found, a new match-action entry is added to a match-action table. Aging-out mechanisms are used for the match-action tables and the EM cache. A multi-hash scheme is used to that supports a very large number of match-action entries.

    Efficient receive interrupt signaling
    8.
    发明授权
    Efficient receive interrupt signaling 有权

    公开(公告)号：US11797333B2

    公开(公告)日：2023-10-24

    申请号：US16710556

    申请日：2019-12-11

    Applicant: Intel Corporation

    Inventor： Linden Cornett ,  Anil Vasudevan ,  Parthasarathy Sarangam ,  Kiran Patil

    IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

    CPC classification number: G06F9/4812 ,  G06F9/5077 ,  G06F2209/5011

    Abstract: Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located. After asserting an interrupt, an RX queue may be auto-masked to prevent generation of additional events when new descriptors are enqueued in the RX queue.

    Technologies for accelerated HTTP processing with hardware acceleration
    10.
    发明授权
    Technologies for accelerated HTTP processing with hardware acceleration 有权

    公开(公告)号：US11451609B2

    公开(公告)日：2022-09-20

    申请号：US16022949

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Parthasarathy Sarangam ,  Manasi Deval ,  Gregory Bowers

    IPC: H04L67/02 ,  H04L69/04 ,  H04L69/166 ,  H04L69/164 ,  H04L9/40

    Abstract: Technologies for accelerated HTTP message processing include a computing device having a network controller. The computing device may generate an HTTP message, frame the HTTP message to generate a transport protocol packet such as a TCP/IP packet or QUIC packet, and pass the transport protocol packet to the network controller. The network controller compresses the HTTP header of the HTTP message, encrypts the compressed HTTP message, and transmits the encrypted message to a remote device. The network controller may segment the transport protocol packet into multiple segmented packets. The network controller may receive transport protocol packets that include encrypted HTTP message. The network controller decrypts the encrypted HTTP message to generate a compressed HTTP message, decompresses the HTTP message, and steers the HTTP message to a receive queue based on contents of an HTTP header. The network controller may coalesce multiple transport protocol packets. Other embodiments are described and claimed.

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