公开(公告)号：US11119704B2

公开(公告)日：2021-09-14

申请号：US16367608

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Mikal Hunsaker ,  Karthi R. Vadivelu ,  Rahul Bhatt ,  Kenneth P. Foust ,  Rajesh Bhaskar ,  Amit Kumar Srivastava

IPC: G06F3/06 ,  G06F13/38 ,  G06F9/54

Abstract: In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

公开(公告)号：US20190188165A1

公开(公告)日：2019-06-20

申请号：US16283498

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Girish C. Venkatraman ,  Rajesh Bhaskar ,  George Vergis ,  John R. Goles

IPC: G06F13/16 ,  G06F13/362 ,  G06F12/06

CPC classification number: G06F13/1694 ,  G06F12/0653 ,  G06F12/0692 ,  G06F13/1657 ,  G06F13/362

Abstract: In embodiments, a device includes an input interface to receive a broadcast command from a host computer, the broadcast command including an access mode indication, and decoding circuitry coupled with the interface. The decoding circuitry is to determine, based at least in part on the received access mode indication, that the broadcast command is directed to access one or more pre-defined setup or control registers of one or more devices, or to access one or more internal registers of the one or more devices, and, in response to the determination, implement the access to the setup or control registers, or to the one or more internal registers. In embodiments, the device is disposed on a memory module coupled to the host computer.

公开(公告)号：US11506702B2

公开(公告)日：2022-11-22

申请号：US17031107

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Asad Azam ,  Amit Kumar Srivastava ,  Enrico Carrieri ,  Rajesh Bhaskar

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/46 ,  G11C29/36 ,  G11C29/08

Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

公开(公告)号：US20220006883A1

公开(公告)日：2022-01-06

申请号：US17476618

申请日：2021-09-16

Applicant: Intel Corporation

Inventor： Amit Srivastava ,  Matthew A. Schnoor ,  Rajesh Bhaskar ,  Aruni P. Nelson ,  Enrico David Carrieri ,  Devon Worrell

IPC: H04L29/06 ,  H04L12/40

Abstract: In one embodiment, an apparatus includes a unified adapter layer and a first bus controller. The unified adapter layer is to receive a first host data packet packetized in accordance with a host protocol and directed to a first device and decode the first host data packet to generate first and second data elements based on the first host data packet, the first device associated with a first device protocol. The first bus controller is coupled to the unified adapter layer and is to be coupled to the first device via a first bus. The first bus controller is to packetize the first data element in accordance with the first device protocol to generate a first device data packet for transmission to the first device in accordance with the first device protocol via the first bus and adjust a bus controller parameter based in part on the second data element. Other embodiments are described and claimed.

公开(公告)号：US10970239B2

公开(公告)日：2021-04-06

申请号：US15970639

申请日：2018-05-03

Applicant: Intel Corporation

Inventor： Rajesh Bhaskar ,  Kenneth Foust ,  George Vergis

IPC: G11C7/10 ,  G06F13/16 ,  G06F13/40 ,  G11C5/02 ,  G06F13/42 ,  G06F1/18 ,  G11C7/22 ,  G11C5/04

Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

公开(公告)号：US20190042473A1

公开(公告)日：2019-02-07

申请号：US15856570

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Rajesh Bhaskar ,  Reshma Lal ,  Siddhartha Chhabra

IPC: G06F12/14 ,  G06F21/78 ,  G06F21/85 ,  G06F21/60 ,  G06F13/28

Abstract: Technologies for secure I/O include a computing device that further includes an I/O controller and a trusted I/O (TIO) mode manager. The TIO mode manager is to program, over a secure routing hardware of the computing device, the I/O controller of the computing device to allow or disallow trusted I/O. The I/O controller is to disable accesses to memory regions associated with one or more programmable I/O registers of an I/O controller of the computing device in response to programming the I/O controller to allow trusted I/O; perform I/O data transfers to or from an I/O device via direct memory access in response to disabling the accesses to the memory regions associated with the one or more programmable I/O registers, wherein the I/O data transfers are protected by a trusted I/O channel; and enable accesses to the address regions associated with the one or more programmable I/O registers in response to programming the I/O controller to disallow trusted I/O.

公开(公告)号：US11334511B2

公开(公告)日：2022-05-17

申请号：US16655511

申请日：2019-10-17

Applicant: Intel Corporation

Inventor： Rajesh Bhaskar ,  Enrico Carrieri ,  Kenneth Foust ,  Janusz Jurski ,  Myron Loewen ,  Matthew A. Schnoor ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F1/10 ,  H04L67/104 ,  G06F13/40 ,  H04L12/40 ,  H04L12/18 ,  H04L29/06

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

公开(公告)号：US20210003629A1

公开(公告)日：2021-01-07

申请号：US17031107

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Asad Azam ,  Amit Kumar Srivastava ,  Enrico Carrieri ,  Rajesh Bhaskar

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/46 ,  G11C29/36 ,  G11C29/08

Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

公开(公告)号：US10853289B2

公开(公告)日：2020-12-01

申请号：US16221962

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Asad Azam ,  Rajesh Bhaskar ,  Mikal Hunsaker ,  Enrico D. Carrieri

IPC: G06F13/36 ,  G06F13/364 ,  H04L12/801 ,  H04L12/835 ,  G06F13/24 ,  G06F13/16 ,  G06F13/42 ,  H04L5/16

Abstract: In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.

公开(公告)号：US20200050571A1

公开(公告)日：2020-02-13

申请号：US16655511

申请日：2019-10-17

Applicant: Intel Corporation

Inventor： Rajesh Bhaskar ,  Enrico Carrieri ,  Kenneth Foust ,  Janusz Jurski ,  Myron Loewen ,  Matthew A. Schnoor ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F13/40 ,  H04L29/08 ,  H04L12/18 ,  H04L12/40 ,  G06F1/10

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.