公开(公告)号：US09859253B1

公开(公告)日：2018-01-02

申请号：US15196937

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Saikumar Jayaraman ,  John S. Guzek ,  Yidnekachew S. Mekonnen

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/522 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/85815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161

Abstract: Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.

公开(公告)号：US20250102744A1

公开(公告)日：2025-03-27

申请号：US18476089

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Feifei Cheng ,  Kumar Abhishek Singh ,  Peter A. Williams ,  Ziyin Lin ,  Fan Fan ,  Yang Wu ,  Saikumar Jayaraman ,  Baris Bicen ,  Darren Vance ,  Anurag Tripathi ,  Divya Pratap ,  Stephanie J. Arouh

IPC: G02B6/42

Abstract: Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the FAU to the PIC die. In another embodiment, a warpage amount of a PIC die is characterized, and a FAU lid with a similar warpage is fabricated, allowing for the FAU to position fibers correctly relative to waveguides in the PIC die. In another embodiment, a FAU has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.

公开(公告)号：US20250004223A1

公开(公告)日：2025-01-02

申请号：US18346116

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Vidya Jayaram ,  Ravindranath V. Mahajan ,  Saikumar Jayaraman

IPC: G02B6/42

Abstract: An apparatus comprising an interposer to couple conductive contacts of a substrate to conductive contacts of an integrated circuit device, wherein the interposer comprises a cavity proximate conductive contacts of the interposer, the conductive contacts of the interposer to couple to conductive contacts of a photonics integrated circuit (PIC).

公开(公告)号：US10522450B1

公开(公告)日：2019-12-31

申请号：US16159861

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Gregorio Murtagian ,  Saikumar Jayaraman

IPC: H01L23/02 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00

Abstract: An electronic device may include a semiconductor package, that may include a package substrate. The package may include a semiconductor die. A plurality of package interconnects may include a first pillar extending from a surface of the package substrate. The electronic device may include a socket that may be configured to couple with the semiconductor package. The socket may include a plurality of socket interconnects configured to engage with the package interconnects. The plurality of socket interconnects may include a first contact, and the first contact may include an arm. The arm of the first contact may be configured to engage with the first pillar, and the arm may be configured to laterally displace when engaged with the first pillar. The engagement of the arm with the first pillar may establish an electrical communication pathway between the semiconductor package and the socket.

公开(公告)号：US10115606B2

公开(公告)日：2018-10-30

申请号：US15139265

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Yuying Wei ,  Arjun Krishnan ,  Suriyakala Ramalingam ,  Yonghao Xiu ,  Beverly J. Canham ,  Sivakumar Nagarajan ,  Saikumar Jayaraman ,  Nisha Ananthakrishnan

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/28 ,  H01L21/56 ,  H01L23/29 ,  H01L23/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.

公开(公告)号：US11769753B2

公开(公告)日：2023-09-26

申请号：US16051065

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： George Vakanas ,  Aastha Uppal ,  Shereen Elhalawaty ,  Aaron McCann ,  Edvin Cetegen ,  Tannaz Harirchian ,  Saikumar Jayaraman

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L23/3736 ,  H01L24/49 ,  H10B12/00

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

公开(公告)号：US09659889B2

公开(公告)日：2017-05-23

申请号：US14136908

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Mihir Oka ,  Xavier Brun ,  Dingying David Xu ,  Edward Prack ,  Kabirkumar Mirpuri ,  Saikumar Jayaraman

IPC: H01L23/00 ,  C08K3/36 ,  C08K3/22 ,  B23K1/20 ,  B23K1/00 ,  B23K26/362 ,  C09D179/02 ,  C08G73/02 ,  B23K101/42

CPC classification number: H01L24/11 ,  B23K1/0016 ,  B23K1/20 ,  B23K26/361 ,  B23K26/362 ,  B23K2101/42 ,  C08G73/0233 ,  C08K3/22 ,  C08K3/36 ,  C08K2003/2241 ,  C09D179/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13347 ,  H01L2224/1339 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  C08L79/04 ,  C08L79/02

Abstract: This disclosure relates generally to generating a solder-on-die using a water-soluble resist, system, and method. Heat may be applied to solder as applied to a hole formed in a water-soluble resist coating, the water-soluble resist coating being on a surface of an initial assembly. The initial assembly may include an electronic component. The surface may be formed, at least in part, by an electrical terminal of the electronic component, the hole being aligned, at least in part, with the electrical terminal. The solder may be reflowed, wherein the solder couples, at least in part, with the electrical terminal.

公开(公告)号：US09247686B2

公开(公告)日：2016-01-26

申请号：US14198129

申请日：2014-03-05

Applicant: Intel Corporation

Inventor： Saikumar Jayaraman ,  Paul A. Koning ,  Ashay Dani

IPC: H05K13/04 ,  H01L23/42 ,  H01L23/427 ,  H01L23/00

CPC classification number: H05K13/0465 ,  H01L23/42 ,  H01L23/4275 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83101 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  Y10T156/10 ,  Y10T428/24926 ,  Y10T428/25 ,  Y10T428/254 ,  Y10T428/256 ,  Y10T428/31917 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01083 ,  H01L2224/29099 ,  H01L2224/0401

Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.

Abstract translation: 本发明的实施方案提供可用作聚合物焊料混合热界面材料的粘合剂基质的各种聚合物基质。 在替代实施方案中，粘合剂基质材料可以是磷光体，全氟醚，聚醚或氨基甲酸酯。 对于一个实施方案，选择粘合剂基质以提供对各种界面的改进的粘合性。 对于替代实施例，选择粘合剂基质以提供低接触电阻。 在替代实施例中，包含易熔和不可熔颗粒的聚合材料可用于需要散热的应用中，并且不限于用于微电子器件的热界面材料。

公开(公告)号：US20180005989A1

公开(公告)日：2018-01-04

申请号：US15196937

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Saikumar Jayaraman ,  John S. Guzek ,  Yidnekachew S. Mekonnen

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/85815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161

Abstract: Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.

公开(公告)号：US20160247774A1

公开(公告)日：2016-08-25

申请号：US15146423

申请日：2016-05-04

Applicant: Intel Corporation

Inventor： Rubayat Mahmud ,  Saikumar Jayaraman ,  Sriram Muthukumar

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02126 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13026 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Abstract translation: 本公开总体上涉及具有多个具有主表面的半导体芯片的晶片，位于多个半导体芯片之一上的金属触点，并且具有侧表面和接触表面，该接触表面基本上平行于主表面，其中 所述接触表面限定所述金属接触件相对于所述主表面的厚度，底部填充层邻接所述多个半导体芯片中的一个和所述金属接触件的侧表面，所述底部填充层具有基本上平行于所述主表面的顶表面 其中所述底部填充层的顶表面相对于所述主表面限定所述底部填充层的厚度，所述底部填充层的厚度不大于所述金属接触件的厚度，以及形成为与所述触点电接触的焊料凸块 表面的金属接触。