公开(公告)号：US20190147640A1

公开(公告)日：2019-05-16

申请号：US16173722

申请日：2018-10-29

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer KP ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  H04N5/369 ,  G06T15/00 ,  G06T15/60 ,  G06T15/10 ,  H04N5/232 ,  H04N13/239 ,  H04N13/344 ,  G06K9/00 ,  G02B27/01

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US20160372027A1

公开(公告)日：2016-12-22

申请号：US15090911

申请日：2016-04-05

Applicant: Intel Corporation

Inventor： Mallari C. Hanchate ,  Ganesh R. S.T. ,  Bharath Kumar ,  Sameer KP

IPC: G09G3/20 ,  G09G3/34

CPC classification number: G09G3/2096 ,  G06F3/1431 ,  G09G3/3406 ,  G09G3/3614 ,  G09G5/006 ,  G09G2300/026 ,  G09G2320/064 ,  G09G2330/021 ,  G09G2330/026 ,  G09G2330/027 ,  G09G2370/10 ,  G09G2370/20

Abstract: Two extended embedded Display Port displays may be enabled by using a single set of panel power sequencing (PPS) signals from a chipset to enable the two embedded Display Port panels. To enhance the user experience, the backlight module brightness is controlled by making use of a pin available on a system on a chip (SOC) and modification of drivers. This helps to save power when only one panel is used. When both panels are used simultaneously, power savings can be achieved by using backlight control signals.

Abstract translation: 两个扩展的嵌入式显示端口显示器可以通过使用来自芯片组的一组面板电源排序（PPS）信号来启用两个嵌入式显示端口面板。 为了增强用户体验，通过利用芯片上的系统（SOC）上可用的引脚和驱动器的修改来控制背光模块的亮度。 这有助于在仅使用一个面板时节省电力。 当两个面板同时使用时，可以通过使用背光控制信号实现功率节省。

公开(公告)号：US11244479B2

公开(公告)日：2022-02-08

申请号：US16919839

申请日：2020-07-02

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US10380039B2

公开(公告)日：2019-08-13

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Satyeshwar Singh ,  Sameer KP ,  Ankur N. Shah ,  Kun Tian ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20220262047A1

公开(公告)日：2022-08-18

申请号：US17666193

申请日：2022-02-07

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US10152822B2

公开(公告)日：2018-12-11

申请号：US15477019

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer KP ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  H04N5/369 ,  G02B27/01 ,  G06T15/10 ,  G06T15/60 ,  G06K9/00 ,  H04N5/232

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US20180286345A1

公开(公告)日：2018-10-04

申请号：US15472900

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Yiting Lee ,  Mathangi Srinivasan ,  Suketu J. Shah ,  Sameer KP ,  Curly Tsao

IPC: G09G5/00

Abstract: Methods for controlling refresh rate during panel self-refresh 2 (PSR2), are described. Those methods and associated devices may include sending, via a source interface controller enabled for PSR2, a display port configuration data (DPCD) value of high, a data transfer request packet to include a low refresh rate target value of a display device; receiving, via the sink interface controller, the DPCD high value; and entering, via the sink interface controller, a low refresh rate at target values when the source interface controller enters static or sleep mode, and wherein the refresh rate is dynamically controlled during PSR2.

公开(公告)号：US20240161356A1

公开(公告)日：2024-05-16

申请号：US18517318

申请日：2023-11-22

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US20220005259A1

公开(公告)日：2022-01-06

申请号：US17481656

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer KP ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  G06K9/00 ,  G02B27/01 ,  G06T15/60 ,  H04N5/232 ,  H04N13/344 ,  G06T15/10 ,  H04N5/369 ,  G06T15/00 ,  H04N13/239

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US20190043442A1

公开(公告)日：2019-02-07

申请号：US16034302

申请日：2018-07-12

Applicant: Intel Corporation

Inventor： Sameer KP ,  Vinay Angadi ,  Yiting Lee ,  Roland Wooster ,  Sagar Karalatti

IPC: G09G5/00 ,  G09G5/04 ,  G09G3/34 ,  G06F17/30

Abstract: A processing unit, device, system and method are described. A processing unit can be configured to access frame data and associated metadata. The processing unit can be configured to send the associated metadata from a processing unit to a display controller on a channel that is different than a channel configured to send the frame data.