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公开(公告)号：US20180129266A1
公开(公告)日：2018-05-10
申请号：US15849838
申请日：2017-12-21
Applicant: Intel Corporation
Inventor： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
CPC classification number: G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3869 , G06F9/3885 , Y02B70/123 , Y02B70/126 , Y02D10/152 , Y02D10/171
Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
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公开(公告)号：US10048965B2
公开(公告)日：2018-08-14
申请号：US15455886
申请日：2017-03-10
Applicant: Intel Corporation
Inventor： Petros Maniatis , Shantanu Gupta , Naveen Kumar
Abstract: A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.
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公开(公告)号：US20170242702A1
公开(公告)日：2017-08-24
申请号：US15455886
申请日：2017-03-10
Applicant: Intel Corporation
Inventor： Petros Maniatis , Shantanu Gupta , Naveen Kumar
CPC classification number: G06F9/30058 , G06F9/3005 , G06F9/3017 , G06F9/35 , G06F9/3836 , G06F9/3867 , G06F9/3877 , G06F9/3887 , G06F12/145 , G06F12/1483 , G06F12/1491 , G06F13/1615 , G06F13/1663 , G06F21/52 , G06F2212/1052 , G06F2221/034
Abstract: A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.
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公开(公告)号：US09606941B2
公开(公告)日：2017-03-28
申请号：US15140427
申请日：2016-04-27
Applicant: Intel Corporation
Inventor： Petros Maniatis , Shantanu Gupta , Naveen Kumar
CPC classification number: G06F9/30058 , G06F9/3005 , G06F9/3017 , G06F9/35 , G06F9/3836 , G06F9/3867 , G06F9/3877 , G06F9/3887 , G06F12/145 , G06F12/1483 , G06F12/1491 , G06F13/1615 , G06F13/1663 , G06F21/52 , G06F2212/1052 , G06F2221/034
Abstract: A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.
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公开(公告)号：US09459871B2
公开(公告)日：2016-10-04
申请号：US13731377
申请日：2012-12-31
Applicant: INTEL CORPORATION
Inventor： Masha Lipshits , Lihu Rappaport , Shantanu Gupta , Franck Sala , Naveen Kumar , Allan D. Knies
CPC classification number: G06F9/30065 , G06F9/325 , G06F9/381 , G06F9/3844
Abstract: A method, system, and computer program product for identifying loop information corresponding to a plurality of loop instructions. The loop instructions are stored into a queue. The loop instructions are replayed from the queue for execution. Loop iteration is counted based on the identified loop information. A determination is made of whether the last iteration of the loop is done. If the last iteration is not done, then embodiments continue replaying the loop instructions, until the last iteration is done.
Abstract translation: 一种用于识别对应于多个循环指令的循环信息的方法，系统和计算机程序产品。 循环指令存储到队列中。 循环指令从队列中重播以供执行。 循环迭代根据识别的循环信息进行计数。 确定循环的最后一次迭代是否完成。 如果最后一次迭代未完成，则实施例继续重播循环指令，直到完成最后一次迭代。
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Patent Agency Ranking
公开(公告)号：US20180129265A1
公开(公告)日：2018-05-10
申请号：US15849836
申请日：2017-12-21
Applicant: Intel Corporation
Inventor： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
CPC classification number: G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3869 , G06F9/3885 , Y02B70/123 , Y02B70/126 , Y02D10/152 , Y02D10/171
Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
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公开(公告)号：US09772674B2
公开(公告)日：2017-09-26
申请号：US14960887
申请日：2015-12-07
Applicant: Intel Corporation
Inventor： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
CPC classification number: G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3869 , G06F9/3885 , Y02B70/123 , Y02B70/126 , Y02D10/152 , Y02D10/171
Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
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公开(公告)号：US20160239438A1
公开(公告)日：2016-08-18
申请号：US15140427
申请日：2016-04-27
Applicant: Intel Corporation
Inventor： Petros Maniatis , Shantanu Gupta , Naveen Kumar
CPC classification number: G06F9/30058 , G06F9/3005 , G06F9/3017 , G06F9/35 , G06F9/3836 , G06F9/3867 , G06F9/3877 , G06F9/3887 , G06F12/145 , G06F12/1483 , G06F12/1491 , G06F13/1615 , G06F13/1663 , G06F21/52 , G06F2212/1052 , G06F2221/034
Abstract: A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.
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公开(公告)号：US10802567B2
公开(公告)日：2020-10-13
申请号：US15849836
申请日：2017-12-21
Applicant: Intel Corporation
Inventor： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
IPC: G06F1/3234 , G06F1/3287 , G06F9/30 , G06F9/38
Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
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公开(公告)号：US20170371397A1
公开(公告)日：2017-12-28
申请号：US15647355
申请日：2017-07-12
Applicant: Intel Corporation
Inventor： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
CPC classification number: G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3869 , G06F9/3885 , Y02B70/123 , Y02B70/126 , Y02D10/152 , Y02D10/171
Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
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